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Searched refs:buildCopy (Results 1 – 25 of 26) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
223 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
236 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
537 MIRBuilder.buildCopy( in lowerCall()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
380 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
440 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
451 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
461 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
471 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
481 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
H A DX86CallLowering.cpp98 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
154 MIRBuilder.buildCopy(Is64Bit ? X86::RAX : X86::EAX, FLI.DemoteRegister); in lowerReturn()
/openbsd/gnu/llvm/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp42 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
61 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0); in getStackAddress()
166 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp102 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
296 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
303 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp91 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
125 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
212 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
234 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
482 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
1152 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1154 MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg); in handleImplicitCallArguments()
1159 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp698 Src = B.buildCopy(Ty, Src).getReg(0); in buildReadFirstLane()
872 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1196 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1603 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0); in applyMappingMAD_64_32()
1604 Register VSrc1 = B.buildCopy(S32, Src1).getReg(0); in applyMappingMAD_64_32()
1653 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1654 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
1702 B.buildCopy(Dst1, Carry); in applyMappingMAD_64_32()
1916 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
2001 B.buildCopy(DstReg, Res[L]); in foldExtractEltToCmpSelect()
[all …]
H A DAMDGPURegBankCombiner.cpp102 Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0); in getAsVgpr()
H A DAMDGPULegalizerInfo.cpp1995 B.buildCopy(Dst, BuildPtr); in legalizeAddrSpaceCast()
2350 B.buildCopy(Dst, Unmerge.getReg(IdxVal)); in legalizeExtractVectorElt()
3275 B.buildCopy(DstReg, LiveIn); in loadInputValue()
5344 B.buildCopy(SGPR01, Temp); in legalizeTrapHsaQueuePtr()
5359 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp263 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
288 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
465 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
523 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1073 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1255 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp981 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
2640 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3605 MIB.buildCopy(DstPtrCopy, DstPtr); in selectMOPS()
3606 MIB.buildCopy(SrcValCopy, SrcOrVal); in selectMOPS()
3607 MIB.buildCopy(SizeCopy, Size); in selectMOPS()
3974 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
5811 MIB.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
5829 MIB.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
5921 MIB.buildCopy({DstReg}, {FrameAddr}); in selectIntrinsic()
6689 auto Copy = MIB.buildCopy({&RC}, {Reg}); in moveScalarRegClass()
[all …]
H A DAArch64PostLegalizerCombiner.cpp232 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp265 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
631 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
635 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp342 MIRBuilder.buildCopy( in translateCompare()
345 MIRBuilder.buildCopy( in translateCompare()
1304 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1353 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1462 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1578 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2150 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
2164 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
2194 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2697 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
H A DCSEMIRBuilder.cpp150 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DCallLowering.cpp765 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1235 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1239 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
H A DMachineIRBuilder.cpp288 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
497 return buildCopy(Res, Op); in buildBoolExtInReg()
556 return buildCopy(Dst, Src); in buildCast()
H A DLegalizerHelper.cpp4515 MIRBuilder.buildCopy(DstReg, SplitSrcs[0]); in fewerElementsVectorReductions()
4524 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorReductions()
5338 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
6752 MIRBuilder.buildCopy(DstReg, Val); in lowerShuffleVector()
6801 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in lowerDynStackAlloc()
6816 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
6817 MIRBuilder.buildCopy(Dst, SPTmp); in lowerDynStackAlloc()
7283 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
7285 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
7338 auto AsInt = MIRBuilder.buildCopy(IntTy, SrcReg); in lowerISFPCLASS()
[all …]
H A DCombinerHelper.cpp166 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
390 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
830 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2043 Builder.buildCopy(DstReg, Reg); in applyCombineI2PToP2I()
4848 B.buildCopy(Dst, LHS); in matchAddOBy0()
4904 MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, ReplaceReg); }; in matchSubAddSameReg()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp54 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DSplitKit.h426 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
H A DSplitKit.cpp536 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, in buildCopy() function in SplitEditor
626 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h522 Builder.buildCopy(DstReg, SrcReg); in replaceRegOrBuildCopy()
H A DMachineIRBuilder.h862 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
/openbsd/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp461 MIRBuilder.buildCopy(ResVReg, Reg); in buildGlobalVariable()

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