/openbsd/gnu/usr.bin/texinfo/doc/ |
H A D | pdfcolor.tex | 4 \def\cmykYellow{0 0 1 0} 8 \def\cmykPeach{0 0.50 0.70 0} 18 \def\cmykRed{0 1 1 0} 24 \def\cmykMagenta{0 1 0 0} 45 \def\cmykBlue{1 1 0 0} 47 \def\cmykCyan{1 0 0 0} 57 \def\cmykGreen{1 0 1 0} 69 \def\cmykBlack{0 0 0 1} 70 \def\cmykWhite{0 0 0 0} 148 \def\makefootline{ [all …]
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/openbsd/gnu/llvm/clang/include/clang/Basic/ |
H A D | StmtNodes.td | 9 def Stmt : StmtNode<?, 1>; 10 def NullStmt : StmtNode<Stmt>; 11 def CompoundStmt : StmtNode<Stmt>; 12 def IfStmt : StmtNode<Stmt>; 13 def SwitchStmt : StmtNode<Stmt>; 14 def WhileStmt : StmtNode<Stmt>; 15 def DoStmt : StmtNode<Stmt>; 16 def ForStmt : StmtNode<Stmt>; 17 def GotoStmt : StmtNode<Stmt>; 20 def BreakStmt : StmtNode<Stmt>; [all …]
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H A D | DeclNodes.td | 12 def Decl : DeclNode<?, "", 1>; 14 def PragmaComment : DeclNode<Decl>; 40 def Binding : DeclNode<Value>; 43 def MSGuid : DeclNode<Value>; 87 def ObjCImpl 99 def AccessSpec : DeclNode<Decl>; 100 def Friend : DeclNode<Decl>; 106 def Import : DeclNode<Decl>; 108 def OMPAllocate : DeclNode<Decl>; 109 def OMPRequires : DeclNode<Decl>; [all …]
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H A D | DiagnosticGroups.td | 21 def ODR : DiagGroup<"odr">; 22 def : DiagGroup<"abi">; 65 def DeprecatedCoroutine : 67 def AlwaysInlineCoroutine : 125 def FloatConversion : 239 def DynamicExceptionSpec 434 def : DiagGroup<"import">; 465 def : DiagGroup<"inline">; 525 def NullPointerArithmetic 542 def FunctionDefInObjCContainer : DiagGroup<"function-def-in-objc-container">; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMSchedule.td | 60 def WriteALU : SchedWrite; 61 def ReadALU : SchedRead; 70 def WriteCMP : SchedWrite; 79 def ReadMUL : SchedRead; 86 def ReadMAC : SchedRead; 89 def WriteDIV : SchedWrite; 92 def WriteLd : SchedWrite; 94 def WriteST : SchedWrite; 97 def WriteBr : SchedWrite; 98 def WriteBrL : SchedWrite; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCSchedule.td | 12 def IIC_IntSimple : InstrItinClass; 13 def IIC_IntGeneral : InstrItinClass; 14 def IIC_IntCompare : InstrItinClass; 15 def IIC_IntISEL : InstrItinClass; 16 def IIC_IntDivD : InstrItinClass; 17 def IIC_IntDivW : InstrItinClass; 18 def IIC_IntMFFS : InstrItinClass; 19 def IIC_IntMFVSCR : InstrItinClass; 20 def IIC_IntMTFSB0 : InstrItinClass; 21 def IIC_IntMTSRD : InstrItinClass; [all …]
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/openbsd/gnu/llvm/llvm/include/llvm/IR/ |
H A D | IntrinsicsHexagonDep.td | 1063 def int_hexagon_A2_abs : 1072 def int_hexagon_A2_add : 1126 def int_hexagon_A2_and : 1159 def int_hexagon_A2_max : 1171 def int_hexagon_A2_min : 1183 def int_hexagon_A2_neg : 1192 def int_hexagon_A2_not : 1198 def int_hexagon_A2_or : 1204 def int_hexagon_A2_orp : 1210 def int_hexagon_A2_sat : [all …]
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H A D | IntrinsicsAArch64.td | 47 def int_aarch64_frint32z 50 def int_aarch64_frint64z 53 def int_aarch64_frint32x 56 def int_aarch64_frint64x 289 def int_aarch64_neon_pmull64 : 514 def int_aarch64_neon_bfmmla 523 def int_aarch64_neon_bfcvt 525 def int_aarch64_neon_bfcvtn 527 def int_aarch64_neon_bfcvtn2 1572 def int_aarch64_sve_prf [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonIntrinsicsV5.td | 16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; 17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; 18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; 19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>; 20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>; 21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>; 83 def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>; 84 def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>; 85 def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>; 227 def: T_RR_pat<A4_orn, int_hexagon_A4_orn>; [all …]
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H A D | HexagonDepITypes.td | 12 def TypeALU32_2op : IType<0>; 15 def TypeALU64 : IType<3>; 16 def TypeCJ : IType<4>; 17 def TypeCR : IType<5>; 28 def TypeCVI_VA : IType<16>; 47 def TypeJ : IType<35>; 48 def TypeLD : IType<36>; 49 def TypeM : IType<37>; 51 def TypeNCJ : IType<39>; 53 def TypeST : IType<41>; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVSchedSyntacoreSCR1.td | 33 def SCR1_ALU : ProcResource<1>; 34 def SCR1_LSU : ProcResource<1>; 35 def SCR1_MUL : ProcResource<1>; 36 def SCR1_DIV : ProcResource<1>; 37 def SCR1_CFU : ProcResource<1>; 127 def : WriteRes<WriteSFB, []>; 131 def : WriteRes<WriteCSR, []>; 132 def : WriteRes<WriteNop, []>; 138 def : ReadAdvance<ReadJmp, 0>; 140 def : ReadAdvance<ReadCSR, 0>; [all …]
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H A D | RISCVSchedule.td | 24 def WriteNop : SchedWrite; 109 def ReadSFB : SchedRead; 112 def ReadJmp : SchedRead; 113 def ReadJalr : SchedRead; 114 def ReadCSR : SchedRead; 115 def ReadMemBase : SchedRead; 203 def : WriteRes<WriteFLD16, []>; 204 def : WriteRes<WriteFMA16, []>; 210 def : WriteRes<WriteFST16, []>; 237 def : WriteRes<WriteSFB, []>; [all …]
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H A D | RISCVSchedSiFive7.td | 12 def SiFive7Model : SchedMachineModel { 167 def : WriteRes<WriteNop, []>; 173 def : ReadAdvance<ReadJmp, 0>; 174 def : ReadAdvance<ReadJalr, 0>; 175 def : ReadAdvance<ReadCSR, 0>; 178 def : ReadAdvance<ReadIALU, 0>; 184 def : ReadAdvance<ReadIDiv, 0>; 186 def : ReadAdvance<ReadIMul, 0>; 202 def : ReadAdvance<ReadFMA32, 0>; 203 def : ReadAdvance<ReadFMA64, 0>; [all …]
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H A D | RISCVScheduleZb.td | 16 def WriteRotateImm : SchedWrite; 17 def WriteRotateImm32 : SchedWrite; 18 def WriteRotateReg : SchedWrite; 99 def : WriteRes<WriteCLZ, []>; 101 def : WriteRes<WriteCTZ, []>; 103 def : WriteRes<WriteCPOP, []>; 105 def : WriteRes<WriteREV8, []>; 106 def : WriteRes<WriteORCB, []>; 112 def : ReadAdvance<ReadCLZ, 0>; 114 def : ReadAdvance<ReadCTZ, 0>; [all …]
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H A D | RISCVSchedRocket.td | 14 def RocketModel : SchedMachineModel { 173 def : WriteRes<WriteCSR, []>; 174 def : WriteRes<WriteNop, []>; 180 def : ReadAdvance<ReadJmp, 0>; 181 def : ReadAdvance<ReadJalr, 0>; 182 def : ReadAdvance<ReadCSR, 0>; 185 def : ReadAdvance<ReadIALU, 0>; 191 def : ReadAdvance<ReadIDiv, 0>; 193 def : ReadAdvance<ReadIMul, 0>; 209 def : ReadAdvance<ReadFMA32, 0>; [all …]
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/openbsd/gnu/llvm/clang/include/clang/AST/ |
H A D | CommentHTMLNamedCharacterReferences.td | 15 def : NCR<"copy", 0x000A9>; 16 def : NCR<"COPY", 0x000A9>; 17 def : NCR<"trade", 0x02122>; 18 def : NCR<"TRADE", 0x02122>; 19 def : NCR<"reg", 0x000AE>; 20 def : NCR<"REG", 0x000AE>; 21 def : NCR<"lt", 0x0003C>; 22 def : NCR<"Lt", 0x0003C>; 23 def : NCR<"LT", 0x0003C>; 24 def : NCR<"gt", 0x0003E>; [all …]
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H A D | CommentCommands.td | 52 def Begin : Command<name> { 57 def End : Command<endCommandName> { 90 def B : InlineCommand<"b">; 91 def C : InlineCommand<"c">; 92 def P : InlineCommand<"p">; 93 def A : InlineCommand<"a">; 94 def E : InlineCommand<"e">; 96 def Em : InlineCommand<"em">; 97 def Emoji : InlineCommand<"emoji">; 100 def Ref : InlineCommand<"ref">; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUSearchableTables.td | 19 def RsrcIntrinsics : GenericTable { 51 def Gfx9BufferFormat : GcnBufferFormatTable { 55 def Gfx10BufferFormat : GcnBufferFormatTable { 64 def getGfx9BufferFormatInfo : SearchIndex { 68 def getGfx10BufferFormatInfo : SearchIndex { 72 def getGfx11PlusBufferFormatInfo : SearchIndex { 217 def SourcesOfDivergence : GenericTable { 376 def : SourceOfDivergence<int_amdgcn_if>; 377 def : SourceOfDivergence<int_amdgcn_else>; 378 def : SourceOfDivergence<int_amdgcn_loop>; [all …]
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H A D | SISchedule.td | 13 def : PredicateProlog<[{ 19 def WriteBranch : SchedWrite; 20 def WriteExport : SchedWrite; 21 def WriteLDS : SchedWrite; 22 def WriteSALU : SchedWrite; 23 def WriteSMEM : SchedWrite; 24 def WriteVMEM : SchedWrite; 25 def WriteBarrier : SchedWrite; 27 def MIVGPRRead : SchedRead; 28 def MIMFMARead : SchedRead; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AVR/ |
H A D | AVRDevices.td | 58 def FeatureSmallStack 112 def FeatureMultiplication 123 def FeatureTinyEncoding 166 def FamilyAVR2 170 def FamilyAVR25 178 def FamilyAVR35 182 def FamilyAVR4 : Family<"avr4", 186 def FamilyAVR5 : Family<"avr5", 194 def FamilyTiny 205 def FamilyXMEGA : Family<"xmega", [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 12 def ALU : FuncUnit; 13 def IMULDIV : FuncUnit; 19 def IIM16Alu : InstrItinClass; 20 def IIPseudo : InstrItinClass; 22 def II_ABS : InstrItinClass; 23 def II_ADDI : InstrItinClass; 24 def II_ADDIU : InstrItinClass; 25 def II_ADDIUPC : InstrItinClass; 26 def II_ADD : InstrItinClass; 27 def II_ADDU : InstrItinClass; [all …]
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H A D | MipsScheduleGeneric.td | 16 def MipsGenericModel : SchedMachineModel { 974 def : InstRW<[GenericWriteFPUCmp], 976 def : InstRW<[GenericWriteFPUCmp], 979 def : InstRW<[GenericWriteFPUL], 982 def : InstRW<[GenericWriteFPUL], 985 def : InstRW<[GenericWriteFPUL], 988 def : InstRW<[GenericWriteFPUL], 991 def : InstRW<[GenericWriteFPUL], 994 def : InstRW<[GenericWriteFPUS], 1157 def : InstRW<[GenericDSPShort], [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.td | 217 def C0 : Ri< 0, "C0">; 218 def C1 : Ri< 1, "C1">; 219 def C2 : Ri< 2, "C2">; 220 def C3 : Ri< 3, "C3">; 221 def C4 : Ri< 4, "C4">; 222 def C5 : Ri< 5, "C5">; 223 def C6 : Ri< 6, "C6">; 224 def C7 : Ri< 7, "C7">; 225 def C8 : Ri< 8, "C8">; 226 def C9 : Ri< 9, "C9">; [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedExynosM4.td | 630 def : InstRW<[WriteST, 683 def : InstRW<[WriteVLD, 688 def : InstRW<[WriteVLD, 692 def : InstRW<[WriteVLD, 711 def : InstRW<[WriteVST, 718 def : InstRW<[WriteVST, 724 def : InstRW<[WriteVST, 839 def : InstRW<[WriteVLD, 842 def : InstRW<[WriteVLD, 871 def : InstRW<[WriteVLD, [all …]
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H A D | AArch64SchedExynosM3.td | 518 def : InstRW<[M3WriteLD, 521 def : InstRW<[M3WriteLB, 533 def : InstRW<[WriteST, 568 def : InstRW<[WriteVLD, 573 def : InstRW<[WriteVLD, 577 def : InstRW<[WriteVLD, 590 def : InstRW<[WriteVST, 597 def : InstRW<[WriteVST, 602 def : InstRW<[WriteVST, 794 def : InstRW<[WriteVST, [all …]
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