| /openbsd/sys/dev/pci/drm/i915/display/ |
| H A D | intel_dpll.c | 327 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
776 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
778 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
783 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
876 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
933 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
1027 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1137 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1585 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1971 const struct dpll *dpll) in vlv_force_pll_on() argument
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| H A D | intel_dpll.h | 11 struct dpll;
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
31 const struct dpll *dpll);
41 struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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| H A D | intel_dpll_mgr.c | 489 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
598 hw_state->dpll, in ibx_dump_hw_state()
2131 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers()
2149 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers()
2169 const struct dpll *clk_div) in bxt_ddi_set_dpll_hw_state()
2240 struct dpll clock; in bxt_ddi_pll_get_freq()
2256 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state()
2267 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state()
4367 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4416 if (dev_priv->display.dpll.mgr) { in intel_dpll_dump_hw_state()
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| H A D | intel_pch_refclk.c | 464 dev_priv->display.dpll.pch_ssc_use = 0; in lpt_init_pch_refclk()
468 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); in lpt_init_pch_refclk()
473 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); in lpt_init_pch_refclk()
478 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); in lpt_init_pch_refclk()
481 if (dev_priv->display.dpll.pch_ssc_use) in lpt_init_pch_refclk()
530 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in ilk_init_pch_refclk()
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| H A D | g4x_dp.h | 21 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
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| H A D | intel_display_core.h | 281 const struct intel_dpll_funcs *dpll; member
516 struct intel_dpll dpll; member
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| H A D | g4x_dp.c | 30 static const struct dpll g4x_dpll[] = {
35 static const struct dpll pch_dpll[] = {
40 static const struct dpll vlv_dpll[] = {
45 static const struct dpll chv_dpll[] = {
51 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) in vlv_get_dpll()
60 const struct dpll *divisor = NULL; in g4x_dp_set_clock()
80 pipe_config->dpll = divisor[i]; in g4x_dp_set_clock()
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| H A D | intel_dvo.c | 416 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init_dev() local
455 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE); in intel_dvo_init_dev()
461 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init_dev()
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| H A D | intel_display.c | 1184 if (i915->display.dpll.mgr) { in intel_encoders_update_prepare()
2796 struct dpll clock; in vlv_crtc_clock_get()
2824 struct dpll clock; in chv_crtc_clock_get()
3822 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
3840 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
3842 struct dpll clock; in i9xx_crtc_clock_get()
3868 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
3910 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
7902 struct dpll clock = { in i830_enable_pipe()
7909 u32 dpll, fp; in i830_enable_pipe() local
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| H A D | intel_dpll_mgr.h | 187 u32 dpll; member
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| H A D | intel_display_debugfs.c | 649 dev_priv->display.dpll.ref_clks.nssc, in i915_shared_dplls_info()
650 dev_priv->display.dpll.ref_clks.ssc); in i915_shared_dplls_info()
652 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in i915_shared_dplls_info()
653 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in i915_shared_dplls_info()
661 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); in i915_shared_dplls_info()
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| H A D | icl_dsi.c | 606 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
612 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
622 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
628 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
658 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
674 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
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| H A D | intel_ddi.c | 1480 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1490 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1496 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1500 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1775 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1780 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1789 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1794 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1879 mutex_lock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1887 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
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| H A D | intel_display_types.h | 638 struct dpll { struct
1170 struct dpll dpll; member
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| H A D | intel_display.h | 36 struct dpll;
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| H A D | intel_pch_display.c | 531 tmp = crtc_state->dpll_hw_state.dpll; in ilk_pch_get_config()
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| H A D | intel_sdvo.c | 1277 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
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| /openbsd/sys/dev/pci/drm/i915/gvt/ |
| H A D | handlers.c | 507 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; in bdw_vgpu_get_dp_bitrate()
538 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; in bxt_vgpu_get_dp_bitrate()
541 struct dpll clock = {0}; in bxt_vgpu_get_dp_bitrate()
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