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Searched refs:dpll_hw_state (Results 1 – 7 of 7) sorted by relevance

/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_dpll.c802 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
803 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
876 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
933 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
1059 crtc_state->dpll_hw_state.fp0 = fp; in ilk_update_pll_dividers()
1060 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_update_pll_dividers()
1137 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1222 crtc_state->dpll_hw_state.dpll_md = in vlv_compute_dpll()
1239 crtc_state->dpll_hw_state.dpll_md = in chv_compute_dpll()
1505 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
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H A Dintel_dpll_mgr.c575 &crtc_state->dpll_hw_state, in ibx_get_dpll()
972 crtc_state->dpll_hw_state.wrpll = in hsw_ddi_wrpll_compute_dpll()
978 &crtc_state->dpll_hw_state); in hsw_ddi_wrpll_compute_dpll()
991 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1079 crtc_state->dpll_hw_state.spll = in hsw_ddi_spll_compute_dpll()
1736 &crtc_state->dpll_hw_state); in skl_ddi_hdmi_pll_dividers()
1837 &crtc_state->dpll_hw_state, in skl_get_dpll()
1841 &crtc_state->dpll_hw_state, in skl_get_dpll()
2172 struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; in bxt_ddi_set_dpll_hw_state() local
4442 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); in verify_single_dpll_state()
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H A Dintel_display.c1190 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
3847 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
3849 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
4626 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
5316 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
5318 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); in intel_pipe_config_compare()
5319 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); in intel_pipe_config_compare()
5321 PIPE_CONF_CHECK_X(dpll_hw_state.spll); in intel_pipe_config_compare()
5326 PIPE_CONF_CHECK_X(dpll_hw_state.div0); in intel_pipe_config_compare()
5327 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); in intel_pipe_config_compare()
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H A Dintel_pch_display.c528 &crtc_state->dpll_hw_state); in ilk_pch_get_config()
531 tmp = crtc_state->dpll_hw_state.dpll; in ilk_pch_get_config()
H A Dintel_crtc_state_dump.c350 intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state); in intel_crtc_state_dump()
H A Dintel_display_types.h1177 struct intel_dpll_hw_state dpll_hw_state; member
H A Dintel_ddi.c3846 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
3968 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()