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Searched refs:dpm_level (Results 1 – 24 of 24) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c203 uint32_t dpm_level, uint32_t *freq) in renoir_get_dpm_clk_limited() argument
212 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
218 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
220 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
223 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
230 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
233 if (dpm_level >= NUM_VCN_DPM_LEVELS) in renoir_get_dpm_clk_limited()
235 *freq = clk_table->VClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
238 if (dpm_level >= NUM_VCN_DPM_LEVELS) in renoir_get_dpm_clk_limited()
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/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c648 uint32_t dpm_level, in smu_v13_0_5_get_dpm_freq_by_index() argument
658 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
660 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
663 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
665 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
668 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
670 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
674 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
676 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_5_get_dpm_freq_by_index()
679 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
H A Dsmu_v13_0_4_ppt.c426 uint32_t dpm_level, in smu_v13_0_4_get_dpm_freq_by_index() argument
436 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
438 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
441 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
446 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
452 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
454 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
457 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
[all …]
H A Dyellow_carp_ppt.c782 uint32_t dpm_level, in yellow_carp_get_dpm_freq_by_index() argument
792 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
794 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
797 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
799 *freq = clk_table->VClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
802 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
804 *freq = clk_table->DClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
808 if (dpm_level >= clk_table->NumDfPstatesEnabled) in yellow_carp_get_dpm_freq_by_index()
810 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in yellow_carp_get_dpm_freq_by_index()
813 if (dpm_level >= clk_table->NumDfPstatesEnabled) in yellow_carp_get_dpm_freq_by_index()
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H A Daldebaran_ppt.c1277 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && in aldebaran_set_performance_level()
1317 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in aldebaran_set_soft_freq_limited_range()
1318 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in aldebaran_set_soft_freq_limited_range()
1321 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in aldebaran_set_soft_freq_limited_range()
1342 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { in aldebaran_set_soft_freq_limited_range()
1383 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in aldebaran_usr_edit_dpm_table()
1384 && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in aldebaran_usr_edit_dpm_table()
H A Dsmu_v13_0_6_ppt.c1444 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && in smu_v13_0_6_set_performance_level()
1491 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && in smu_v13_0_6_set_soft_freq_limited_range()
1492 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in smu_v13_0_6_set_soft_freq_limited_range()
1495 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_v13_0_6_set_soft_freq_limited_range()
1515 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { in smu_v13_0_6_set_soft_freq_limited_range()
1560 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && in smu_v13_0_6_usr_edit_dpm_table()
1561 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) in smu_v13_0_6_usr_edit_dpm_table()
H A Dsmu_v13_0.c2322 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in smu_v13_0_od_edit_dpm_table()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr_smu_msg.c259 … dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level) in dcn30_smu_get_dpm_freq_by_index() argument
264 uint32_t param = (clk << 16) | dpm_level; in dcn30_smu_get_dpm_freq_by_index()
266 smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level); in dcn30_smu_get_dpm_freq_by_index()
H A Ddcn30_clk_mgr_smu_msg.h43 …dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c548 uint32_t dpm_level, uint32_t *freq) in vangogh_get_dpm_clk_limited() argument
557 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
559 *freq = clk_table->SocClocks[dpm_level]; in vangogh_get_dpm_clk_limited()
562 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
564 *freq = clk_table->VcnClocks[dpm_level].vclk; in vangogh_get_dpm_clk_limited()
567 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
569 *freq = clk_table->VcnClocks[dpm_level].dclk; in vangogh_get_dpm_clk_limited()
573 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
575 *freq = clk_table->DfPstateTable[dpm_level].memclk; in vangogh_get_dpm_clk_limited()
579 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
[all …]
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c356 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
367 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
369 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
380 if (dpm_table->dpm_level[i - 1].enabled) in phm_get_dpm_level_enable_mask_value()
451 if (value == dpm_table->dpm_level[i].value) { in phm_find_boot_level()
H A Dpp_psm.c295 hwmgr->dpm_level = hwmgr->request_dpm_level; in psm_adjust_power_state_dynamic()
297 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in psm_adjust_power_state_dynamic()
H A Dvega12_hwmgr.c2384 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega12_apply_clocks_adjust_rules()
2389 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2408 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega12_apply_clocks_adjust_rules()
2413 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2452 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2471 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2490 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2509 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
H A Dppatomctrl.h320 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
H A Dvega20_hwmgr.c3766 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega20_apply_clocks_adjust_rules()
3771 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3790 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega20_apply_clocks_adjust_rules()
3795 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3850 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3869 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3888 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3907 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
H A Dhwmgr.c87 hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in hwmgr_early_init()
H A Dppatomctrl.c686 uint16_t dpm_level, in atomctrl_calculate_voltage_evv_on_sclk() argument
735 switch (dpm_level) { in atomctrl_calculate_voltage_evv_on_sclk()
H A Dvega10_hwmgr.c4366 …if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE… in vega10_dpm_force_dpm_level()
4368 …else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PR… in vega10_dpm_force_dpm_level()
4702 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) in vega10_emit_clock_levels()
4847 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) in vega10_print_clock_levels()
H A Dsmu7_hwmgr.c3270 …if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE… in smu7_force_dpm_level()
3272 …else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PR… in smu7_force_dpm_level()
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/
H A Damdgpu_smu.c390 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_restore_dpm_user_profile()
781 smu->smu_dpm.dpm_level, in smu_late_init()
1142 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in smu_sw_init()
1807 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { in smu_enable_umd_pstate()
1810 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; in smu_enable_umd_pstate()
1875 if (smu_dpm_ctx->dpm_level != level) { in smu_adjust_power_state_dynamic()
1883 smu_dpm_ctx->dpm_level = level; in smu_adjust_power_state_dynamic()
1886 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && in smu_adjust_power_state_dynamic()
1935 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); in smu_handle_dpm_task()
1966 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && in smu_switch_power_profile()
[all …]
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/
H A Damd_powerplay.c364 if (!(hwmgr->dpm_level & profile_mode_mask)) { in pp_dpm_en_umd_pstate()
367 hwmgr->saved_dpm_level = hwmgr->dpm_level; in pp_dpm_en_umd_pstate()
388 if (level == hwmgr->dpm_level) in pp_dpm_force_performance_level()
406 return hwmgr->dpm_level; in pp_dpm_get_performance_level()
713 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_dpm_force_clock_level()
873 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_set_power_profile_mode()
962 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_switch_power_profile()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/
H A Dhwmgr.h63 struct vi_dpm_level dpm_level[]; member
764 enum amd_dpm_forced_level dpm_level; member
/openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h364 enum amd_dpm_forced_level dpm_level; member
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c2883 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_UVDDPM)) in ci_update_uvd_smc_table()
2915 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_VCEDPM)) in ci_update_vce_smc_table()