| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 126 .dppclk_mhz = 1200.0,
135 .dppclk_mhz = 1200.0,
144 .dppclk_mhz = 1200.0,
153 .dppclk_mhz = 1200.0,
162 .dppclk_mhz = 1200.0,
370 .dppclk_mhz = 556.0,
379 .dppclk_mhz = 625.0,
388 .dppclk_mhz = 625.0,
397 .dppclk_mhz = 1112.0,
406 .dppclk_mhz = 1250.0,
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 121 .dppclk_mhz = 1015.0,
133 .dppclk_mhz = 1015.0,
145 .dppclk_mhz = 1015.0,
157 .dppclk_mhz = 1015.0,
169 .dppclk_mhz = 1015.0,
357 s[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_update_bw_bounding_box()
458 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_calculate_wm_and_dlg_fp()
462 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
466 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_calculate_wm_and_dlg_fp()
467 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg_fp()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 107 .dppclk_mhz = 1200.0,
116 .dppclk_mhz = 1200.0,
125 .dppclk_mhz = 1200.0,
134 .dppclk_mhz = 1200.0,
143 .dppclk_mhz = 1200.0,
211 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn314_update_bw_bounding_box_fpu()
212 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
247 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : in dcn314_update_bw_bounding_box_fpu()
248 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 226 .dppclk_mhz = 513.0,
237 .dppclk_mhz = 642.0,
248 .dppclk_mhz = 734.0,
337 .dppclk_mhz = 513.0,
348 .dppclk_mhz = 642.0,
359 .dppclk_mhz = 734.0,
448 .dppclk_mhz = 513.0,
459 .dppclk_mhz = 642.0,
470 .dppclk_mhz = 734.0,
1955 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) in dcn20_cap_soc_clocks()
[all …]
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| H A D | display_rq_dlg_calc_20.c | 813 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml20_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_20v2.c | 813 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 112 .dppclk_mhz = 1720.0,
373 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) in build_synthetic_soc_states()
374 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in build_synthetic_soc_states()
413 if (max_clk_data.dppclk_mhz == 0) in build_synthetic_soc_states()
414 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; in build_synthetic_soc_states()
427 entry.dppclk_mhz = max_clk_data.dppclk_mhz; in build_synthetic_soc_states()
712 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn321_update_bw_bounding_box_fpu()
713 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
722 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
810 dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 118 .dppclk_mhz = 300.0,
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
238 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
326 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 260 .dppclk_mhz = 640,
268 .dppclk_mhz = 739,
276 .dppclk_mhz = 960,
284 .dppclk_mhz = 1200,
292 .dppclk_mhz = 1372,
517 bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i]; in dcn315_clk_mgr_helper_populate_bw_params()
533 …bw_params->clk_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevel… in dcn315_clk_mgr_helper_populate_bw_params()
552 if (!bw_params->clk_table.entries[i].dppclk_mhz) in dcn315_clk_mgr_helper_populate_bw_params()
553 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 117 .dppclk_mhz = 300.0,
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
234 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
321 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 130 .dppclk_mhz = 300.0,
554 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
558 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
562 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
563 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
610 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_update_max_clk()
660 dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn30_bb_max_clk->max_dppclk_mhz; in dcn30_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 123 .dppclk_mhz = 2150.0,
2250 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2332 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn32_patch_dpm_table()
2477 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) in build_synthetic_soc_states()
2478 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in build_synthetic_soc_states()
2517 if (max_clk_data.dppclk_mhz == 0) in build_synthetic_soc_states()
2518 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz; in build_synthetic_soc_states()
2531 entry.dppclk_mhz = max_clk_data.dppclk_mhz; in build_synthetic_soc_states()
2807 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn32_update_bw_bounding_box_fpu()
2818 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; in dcn32_update_bw_bounding_box_fpu()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 628 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn314_clk_mgr_helper_populate_bw_params()
644 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn314_clk_mgr_helper_populate_bw_params()
654 …bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK… in dcn314_clk_mgr_helper_populate_bw_params()
676 if (!bw_params->clk_table.entries[i].dppclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
677 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
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| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 35 uint32_t dppclk_mhz; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 168 double dppclk_mhz; member
549 double dppclk_mhz; member
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| H A D | display_mode_vba.c | 68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
401 mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz; in fetch_socbb_params()
707 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz; in fetch_pipe_params()
1109 if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0) in ModeSupportAndSystemConfiguration()
1110 mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz; in ModeSupportAndSystemConfiguration()
1112 mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_lib.c | 278 dml_print("DML PARAMS: dppclk_mhz = %3.2f\n", clks_cfg->dppclk_mhz); in dml_log_pipe_params()
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| H A D | dml1_display_rq_dlg_calc.c | 1019 double dppclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_resource.c | 147 .dppclk_mhz = 300.0,
158 .dppclk_mhz = 1200.0,
169 .dppclk_mhz = 1200.0,
180 .dppclk_mhz = 1200.0,
191 .dppclk_mhz = 1200.0,
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| /openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 92 unsigned int dppclk_mhz; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 230 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn32_init_clocks()
232 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn32_init_clocks()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 155 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 539 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn316_clk_mgr_helper_populate_bw_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 610 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn31_clk_mgr_helper_populate_bw_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 2121 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2122 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
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