| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 119 .dtbclk_mhz = 1564.0,
335 if (max_clk_limit->dtbclk_mhz != 0) in override_max_clk_values()
336 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz; in override_max_clk_values()
377 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz) in build_synthetic_soc_states()
378 max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in build_synthetic_soc_states()
428 entry.dtbclk_mhz = max_clk_data.dtbclk_mhz; in build_synthetic_soc_states()
816 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn321_update_bw_bounding_box_fpu()
817 dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; in dcn321_update_bw_bounding_box_fpu()
819 dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in dcn321_update_bw_bounding_box_fpu()
821 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn321_update_bw_bounding_box_fpu()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 130 .dtbclk_mhz = 625.0,
139 .dtbclk_mhz = 625.0,
148 .dtbclk_mhz = 625.0,
157 .dtbclk_mhz = 625.0,
166 .dtbclk_mhz = 625.0,
374 .dtbclk_mhz = 625.0,
383 .dtbclk_mhz = 625.0,
392 .dtbclk_mhz = 625.0,
401 .dtbclk_mhz = 625.0,
637 s[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 111 .dtbclk_mhz = 600.0,
120 .dtbclk_mhz = 600.0,
129 .dtbclk_mhz = 600.0,
138 .dtbclk_mhz = 600.0,
147 .dtbclk_mhz = 600.0,
252 clock_limits[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 263 .dtbclk_mhz = 600,
271 .dtbclk_mhz = 600,
279 .dtbclk_mhz = 600,
287 .dtbclk_mhz = 600,
295 .dtbclk_mhz = 600,
508 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
558 if (!bw_params->clk_table.entries[i].dtbclk_mhz) in dcn315_clk_mgr_helper_populate_bw_params()
559 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
565 ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz); in dcn315_clk_mgr_helper_populate_bw_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 329 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn302_fpu_update_bw_bounding_box()
330 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz; in dcn302_fpu_update_bw_bounding_box()
332 dcn3_02_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in dcn302_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 324 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn303_fpu_update_bw_bounding_box()
325 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz; in dcn303_fpu_update_bw_bounding_box()
327 dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in dcn303_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 619 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
658 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
682 if (!bw_params->clk_table.entries[i].dtbclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
683 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 130 .dtbclk_mhz = 1564.0,
2350 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; in dcn32_patch_dpm_table()
2439 if (max_clk_limit->dtbclk_mhz != 0) in override_max_clk_values()
2440 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz; in override_max_clk_values()
2481 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz) in build_synthetic_soc_states()
2482 max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in build_synthetic_soc_states()
2532 entry.dtbclk_mhz = max_clk_data.dtbclk_mhz; in build_synthetic_soc_states()
2912 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn32_update_bw_bounding_box_fpu()
2913 dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; in dcn32_update_bw_bounding_box_fpu()
2915 dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; in dcn32_update_bw_bounding_box_fpu()
[all …]
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 361 s[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn301_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 90 unsigned int dtbclk_mhz; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn32_init_clocks()
198 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = in dcn32_init_clocks()
623 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_update_clocks()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 169 double dtbclk_mhz; member
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| H A D | display_mode_vba.c | 406 mode_lib->vba.DTBCLKPerState[i] = soc->clock_limits[i].dtbclk_mhz; in fetch_socbb_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 662 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; in dcn30_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 2387 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; in construct_low_pstate_lvl()
2441 s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn21_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.c | 744 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_initialize_min_clocks()
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