| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 572 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
587 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
629 { .fclk = 400, .memclk = 400, .voltage = 2800 },
630 { .fclk = 400, .memclk = 400, .voltage = 2800 },
631 { .fclk = 400, .memclk = 400, .voltage = 2800 },
632 { .fclk = 400, .memclk = 400, .voltage = 2800 }
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| H A D | dcn301_smu.h | 32 uint32_t fclk; member
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| /openbsd/sys/arch/armv7/omap/ |
| H A D | prcm.c | 418 uint32_t fclk, iclk, fmask, imask, mbit; in prcm_v3_enablemodule() local
431 fclk = bus_space_read_4(sc->sc_iot, sc->sc_prcm, freg); in prcm_v3_enablemodule()
432 bus_space_write_4(sc->sc_iot, sc->sc_prcm, freg, fclk | mbit); in prcm_v3_enablemodule()
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| /openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu11_driver_if_vangogh.h | 114 uint32_t fclk; member
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| /openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu12/ |
| H A D | smu_v12_0.c | 400 &smu->smu_table.boot_values.fclk); in smu_v12_0_get_vbios_bootup_values()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 499 !dc->work_arounds.clock_update_disable_mask.fclk) { in dcn32_update_clocks()
573 !dc->work_arounds.clock_update_disable_mask.fclk) { in dcn32_update_clocks()
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| /openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 581 *freq = clk_table->DfPstateTable[dpm_level].fclk; in vangogh_get_dpm_clk_limited()
947 clock_limit = smu->smu_table.boot_values.fclk; in vangogh_get_dpm_ultimate_freq()
2242 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; in vangogh_get_dpm_clock_table()
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| H A D | smu_v11_0.c | 617 &smu->smu_table.boot_values.fclk); in smu_v11_0_get_vbios_bootup_values()
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| H A D | arcturus_ppt.c | 400 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in arcturus_set_default_dpm_table()
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| H A D | sienna_cichlid_ppt.c | 1009 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in sienna_cichlid_set_default_dpm_table()
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| /openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 298 uint32_t fclk; member
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| /openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 736 clock_limit = smu->smu_table.boot_values.fclk; in smu_v13_0_5_get_dpm_ultimate_freq()
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| H A D | smu_v13_0.c | 661 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; in smu_v13_0_get_vbios_bootup_values()
671 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; in smu_v13_0_get_vbios_bootup_values()
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| H A D | smu_v13_0_4_ppt.c | 761 clock_limit = smu->smu_table.boot_values.fclk; in smu_v13_0_4_get_dpm_ultimate_freq()
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| H A D | yellow_carp_ppt.c | 870 clock_limit = smu->smu_table.boot_values.fclk; in yellow_carp_get_dpm_ultimate_freq()
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| H A D | aldebaran_ppt.c | 377 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in aldebaran_set_default_dpm_table()
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| H A D | smu_v13_0_7_ppt.c | 644 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v13_0_7_set_default_dpm_table()
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| H A D | smu_v13_0_0_ppt.c | 654 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v13_0_0_set_default_dpm_table()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/ |
| H A D | dc.h | 287 uint8_t fclk : 1; member
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