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Searched refs:getCondCode (Results 1 – 17 of 17) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp751 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
761 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
841 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
847 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
875 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
883 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
915 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
941 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
H A DSIISelLowering.cpp4951 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic()
4981 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
5021 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h812 SDValue getCondCode(ISD::CondCode Cond);
1178 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1179 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1190 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
1209 False, getCondCode(Cond));
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp940 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
1025 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1047 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
1050 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
1883 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1968 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
H A DLegalizeIntegerTypes.cpp4954 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5012 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
5041 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
5060 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
5077 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
H A DLegalizeDAG.cpp3639 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3784 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3816 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
H A DTargetLowering.cpp10400 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
10413 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
H A DSelectionDAG.cpp1900 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
H A DSelectionDAGBuilder.cpp7429 Opers.push_back(DAG.getCondCode(Condition)); in visitConstrainedFPIntrinsic()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2128 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
4621 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT()
4672 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerSELECT()
4698 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerBRCOND()
8676 ISD::CondCode getCondCode() const { return CCode; } in getCondCode() function in __anona89954840e11::CmpOpInfo
8725 ISD::CondCode RefCond = Op0.getCondCode(); in verifyCompareConds()
8726 ISD::CondCode AssistCode = Op1.getCondCode(); in verifyCompareConds()
9968 CC = DAG.getCondCode(CCVal); in combine_CC()
9989 CC = DAG.getCondCode(CCVal); in combine_CC()
10007 CC = DAG.getCondCode(CCVal); in combine_CC()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp954 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonf1d18e4d0111::ARMOperand
2429 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2436 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2443 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2451 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2458 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2485 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2486 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2538 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
3908 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp625 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anonee8849df0111::AArch64Operand
1883 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2468 OS << "<condcode " << getCondCode() << ">"; in print()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp17882 N->getOperand(2), Splat, DAG.getCondCode(CC)); in tryConvertSVEWideCompare()
18263 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in performIntrinsicCombine()
18269 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in performIntrinsicCombine()
18275 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in performIntrinsicCombine()
18281 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in performIntrinsicCombine()
18287 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in performIntrinsicCombine()
18293 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performIntrinsicCombine()
18298 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine()
20574 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
22997 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)}); in convertFixedMaskToScalableVector()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6747 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
9231 DAG.getCondCode(ISD::SETNE)); in LowerTruncatei1()
10376 DAG.getCondCode(CC)); in LowerFSETCC()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3532 DAG.getCondCode(CC)); in LowerSETCC()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24597 SDValue CC = DAG.getCondCode(Cond); in splitIntVSETCC()