Searched refs:getWavefrontSize (Results 1 – 20 of 20) sorted by relevance
319 const unsigned WaveSize = getWavefrontSize(); in getMaxLocalMemSizeWithWaveCount()343 const unsigned WaveSize = getWavefrontSize(); in getOccupancyWithLocalMemSize()390 return std::pair(1, getWavefrontSize()); in getDefaultFlatWorkGroupSize()592 return getWavefrontSize() == 32 ? AMDGPUDwarfFlavour::Wave32 in getAMDGPUDwarfFlavour()
202 unsigned getWavefrontSize() const { in getWavefrontSize() function
1276 return getWavefrontSize() == 32; in isWave32()1280 return getWavefrontSize() == 64; in isWave64()
501 Type *const WaveTy = B.getIntNTy(ST->getWavefrontSize()); in optimizeAtomic()553 Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1); in optimizeAtomic()
82 if (ST->getWavefrontSize() == 64) { in requiresWorkAroundForInst()93 assert(ST->getWavefrontSize() == 32); in requiresWorkAroundForInst()
698 STM.getMaxWaveScratchSize() / STM.getWavefrontSize(); in getSIProgramInfo()893 ProgInfo.ScratchSize * STM.getWavefrontSize(), 1ULL << ScratchAlignShift); in getSIProgramInfo()
207 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()904 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
99 ST->getWavefrontSize(); in isLaneMaskReg()
380 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPRLane()
748 const unsigned WavefrontSize = ST.getWavefrontSize(); in lowerInitExec()
1331 unsigned N = ST.getWavefrontSize(); in fold_wavefrontsize()
1323 if (DstTy.getSizeInBits() != STI.getWavefrontSize()) in selectIntrinsicCmp()1383 if (Size != STI.getWavefrontSize()) in selectBallot()1720 if (WGSize <= STI.getWavefrontSize()) { in selectSBarrier()
579 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
4947 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerICMPIntrinsic()4978 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerFCMPIntrinsic()6995 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(), in LowerINTRINSIC_WO_CHAIN()8070 if (WGSize <= ST.getWavefrontSize()) in LowerINTRINSIC_VOID()13043 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass in getRegClassFor()13129 return hasCFUser(V, Visited, Subtarget->getWavefrontSize()); in requiresUniformRegister()
1459 Offset *= ST.getWavefrontSize(); in buildSpillLoadStore()
6660 unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64 in lowerSelect()7512 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2; in getScratchRsrcWords23()
5732 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize()); in legalizeIntrinsic()
190 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
821 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { in getWavefrontSize() function914 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI)); in getWavesPerWorkGroup()