| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | soc15.h | 37 u32 hwip; member
46 u32 hwip; member
53 uint32_t hwip; member
60 uint32_t hwip; member
70 uint32_t hwip; member
79 uint32_t hwip; member
91 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.…
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| H A D | soc15_common.h | 40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ argument
146 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
148 #define RREG32_RLC_NO_KIQ(reg, hwip) \ argument
149 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
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| H A D | amdgpu_imu.h | 42 u32 hwip; member
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| H A D | amdgpu_virt.h | 360 u32 acc_flags, u32 hwip, u32 xcc_id);
362 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
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| H A D | amdgpu_virt.c | 949 u32 acc_flags, u32 hwip, in amdgpu_virt_get_rlcg_reg_access_flag() argument
954 switch (hwip) { in amdgpu_virt_get_rlcg_reg_access_flag()
1078 u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_wreg() argument
1086 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { in amdgpu_sriov_wreg()
1098 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_rreg() argument
1106 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) in amdgpu_sriov_rreg()
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| H A D | amdgpu_ras.h | 335 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ argument
336 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
346 uint32_t hwip; member
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| H A D | soc15.c | 421 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
423 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
457 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
462 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
475 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
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| H A D | imu_v11_0_3.c | 117 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_rlc_ram_register_setting()
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| H A D | soc21.c | 310 if (!adev->reg_offset[en->hwip][en->inst]) in soc21_read_register()
312 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
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| H A D | nv.c | 397 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
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| H A D | imu_v11_0.c | 326 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_imu_rlc_ram()
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| H A D | amdgpu_ras.c | 3251 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_memory_id_field()
3275 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_err_cnt_field()
3352 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, in amdgpu_ras_inst_reset_ras_error_count()
3355 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, in amdgpu_ras_inst_reset_ras_error_count()
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| H A D | gfx_v9_4_3.c | 1363 adev, entry->hwip, entry->instance) : in gfx_v9_4_3_check_rlcg_range()
1365 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + in gfx_v9_4_3_check_rlcg_range()
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| H A D | gfx_v9_0.c | 4929 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in gfx_v9_0_check_rlcg_range()
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| H A D | gfx_v10_0.c | 7929 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in gfx_v10_0_check_rlcg_range()
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| /openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
| H A D | common_baco.h | 47 uint32_t hwip; member
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| H A D | common_baco.c | 112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] in soc15_baco_program_registers()
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