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Searched refs:isCopy (Results 1 – 25 of 79) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp271 if (!CopyUse.isCopy()) in foldVGPRCopyIntoRegSequence()
753 if (MI->isCopy()) { in runOnMachineFunction()
796 AllAGPRUses &= (UseMI->isCopy() && in processPHINode()
799 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
909 if (Inst->isCopy() || Inst->isRegSequence()) { in analyzeVGPRToSGPRCopy()
911 if (!Inst->isCopy() || in analyzeVGPRToSGPRCopy()
923 (Inst->isCopy() && Inst->getOperand(0).getReg() == AMDGPU::SCC)) { in analyzeVGPRToSGPRCopy()
1073 if (!MI.isCopy()) in fixSCCCopies()
H A DGCNNSAReassign.cpp214 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) in CheckNSA()
221 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg) in CheckNSA()
H A DSIFoldOperands.cpp644 if (FoldingImmLike && UseMI->isCopy()) { in foldOperand()
703 if (UseMI->isCopy() && OpToFold.isReg() && in foldOperand()
1571 if (!SubDef || !SubDef->isCopy() || SubDef->getOperand(1).getSubReg()) in tryFoldRegSequence()
1579 while (UseMI->isCopy() && !Op->getSubReg()) { in tryFoldRegSequence()
1657 if (!Copy || !Copy->isCopy()) in tryFoldLCSSAPhi()
1706 if (!I->isCopy() && !I->isRegSequence()) in tryFoldLoad()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp163 if (MI->isCopy() && usesRegClass(MI->getOperand(1), in getPrefSPRLane()
241 if (MI->isCopy()) { in optimizeSDPattern()
262 if (EC && EC->isCopy() && in optimizeSDPattern()
325 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()
H A DThumb2ITBlockPass.cpp123 static bool isCopy(MachineInstr *MI) { in isCopy() function
139 if (!isCopy(MI)) in MoveCopyOutOfITBlock()
H A DMLxExpansionPass.cpp126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
336 if (MI->isPosition() || MI->isImplicitDef() || MI->isCopy()) in ExpandFPMLxInstructions()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp242 return MI.isCopy() || (!DisableAdvCopyOpt && in isCoalescableCopy()
851 assert(MI.isCopy() && "Expected copy instruction"); in CopyRewriter()
1409 assert(MI.isCopy() && "expected a COPY machine instruction"); in foldRedundantCopy()
1454 assert(MI.isCopy() && "expected a COPY machine instruction"); in foldRedundantNAPhysCopy()
1672 if (!MI->isCopy()) { in runOnMachineFunction()
1735 if (MI->isCopy() && (foldRedundantCopy(*MI, CopySrcMIs) || in runOnMachineFunction()
1822 assert(Def->isCopy() && "Invalid definition"); in getNextSourceFromCopy()
2070 if (Def->isCopy()) in getNextSourceImpl()
H A DRegAllocScore.cpp102 if (MI.isCopy()) { in calculateRegAllocScore()
H A DMachineSink.cpp273 if (!MI.isCopy()) in INITIALIZE_PASS_DEPENDENCY()
595 if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI)) in isWorthBreakingCriticalEdge()
1248 if (!MI.isCopy()) { in SinkIntoCycle()
1491 if (MI.getMF()->getFunction().getSubprogram() && MI.isCopy()) in SinkInstruction()
1511 assert(MI.isCopy()); in SalvageUnsunkDebugUsersOfCopy()
1816 if (!MI.isCopy() || !MI.getOperand(0).isRenamable()) { in tryToSinkCopy()
H A DTwoAddressInstructionPass.cpp230 if (!Def || !Def->isCopy()) in isRevCopyChain()
273 if (MI.isCopy()) { in isCopyToReg()
480 if (MI->isCopy()) { in removeClobberedSrcRegMap()
832 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) in rescheduleMIBelowKill()
878 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) in rescheduleMIBelowKill()
974 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) in isDefTooClose()
1022 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) in rescheduleKillAboveMI()
H A DOptimizePHIs.cpp118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
H A DCodeGenCommonISel.cpp56 if (!MI.isCopy() && !MI.isImplicitDef()) { in MIIsInTerminatorSequence()
H A DLiveRangeShrink.cpp200 if (!DefInstr.isCopy()) in runOnMachineFunction()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64StackTaggingPreRA.cpp188 } else if (UseI.isCopy() && UseI.getOperand(0).getReg().isVirtual()) { in uncheckUsesOf()
285 if (UseI.isCopy()) { in findFirstSlotCandidate()
H A DAArch64RedundantCopyElimination.cpp322 if (PredI->isCopy()) { in optimizeBlock()
378 bool IsCopy = MI->isCopy(); in optimizeBlock()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp74 if (!MI->isCopy()) in visitMBB()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp354 if (MI->isCopy() && MI->getOperand(1).getReg().isPhysical()) { in apply()
362 if (MO.isUse() && !MI->isCopy() && in apply()
460 if (DstInst->isCopy()) in adjustSchedDependency()
468 if ((DstInst->isRegSequence() || DstInst->isCopy())) { in adjustSchedDependency()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86LowerTileCopy.cpp79 if (!MI.isCopy()) in runOnMachineFunction()
H A DX86FastPreTileConfig.cpp233 if (UseMI->isCopy()) in reload()
257 if (UseMI->isCopy()) { in reload()
298 } else if (MI->isCopy()) { in getShape()
H A DX86FastTileConfig.cpp88 if (MI.isDebugInstr() || MI.isCopy() || MI.getNumOperands() < 3 || in isTileDef()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp118 if (MI->isCopy() && MI->getOperand(0).isReg() && in optimizeBlock()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp544 if (!Copy->isCopy()) in lookThroughCRCopy()
620 if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() || in splitBlockOnBinaryCROp()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineInstr.h1344 bool isCopy() const {
1349 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1359 return isCopy() || isSubregToReg();
1364 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp95 if (!MI.isCopy()) in foldSimpleCrossClassCopies()
/openbsd/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp238 assert(I->isCopy() && "Copy instruction is expected"); in copyPhysReg()

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