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Searched refs:isSMRD (Results 1 – 7 of 7) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInsertHardClauses.cpp148 if (SIInstrInfo::isSMRD(MI)) in getHardClauseType()
H A DGCNHazardRecognizer.cpp190 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()
332 if (SIInstrInfo::isSMRD(*MI)) in PreEmitNoopsCommon()
611 return !SIInstrInfo::isSMRD(*MI); in breaksSMEMSoftClause()
624 bool IsSMRD = TII.isSMRD(*MEM); in checkSoftClauseHazards()
1147 if (!SIInstrInfo::isSALU(*MI) && !SIInstrInfo::isSMRD(*MI)) in fixVMEMtoScalarWriteHazards()
1225 return SIInstrInfo::isSMRD(I) && I.readsRegister(SDSTReg, TRI); in fixSMEMtoVectorWriteHazards()
H A DSIFormMemoryClauses.cpp102 return SIInstrInfo::isSMRD(MI); in isSMEMClauseInst()
H A DSIPreEmitPeephole.cpp327 if (TII->isSMRD(MI) || TII->isVMEM(MI) || TII->isFLAT(MI) || in mustRetainExeczBranch()
H A DSIInstrInfo.h482 static bool isSMRD(const MachineInstr &MI) { in isSMRD() function
486 bool isSMRD(uint16_t Opcode) const { in isSMRD() function
H A DSIInstrInfo.cpp214 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
415 if (isSMRD(LdSt)) { in getMemOperandsWithOffsetWidth()
3325 return !isFLAT(MIb) && !isSMRD(MIb); in areMemAccessesTriviallyDisjoint()
3328 if (isSMRD(MIa)) { in areMemAccessesTriviallyDisjoint()
3329 if (isSMRD(MIb)) in areMemAccessesTriviallyDisjoint()
3663 if (MI.mayStore() && isSMRD(MI)) in hasUnwantedEffectsWhenEXECEmpty()
4086 SIInstrInfo::isSMRD(MI)) in shouldReadExec()
4584 if (isSMRD(MI)) { in verifyInstruction()
5848 if (isSMRD(MI)) { in legalizeOperands()
7527 return isSMRD(Opc); in isLowLatencyInstruction()
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H A DSIInsertWaitcnts.cpp1434 } else if (TII->isSMRD(Inst)) { in updateEventWaitcntAfter()
1623 if (TII->isSMRD(Inst)) { in insertWaitcntInBlock()