/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.h | 85 if (isShiftedMask_64(Val)) { in isRunOfOnes64() 93 if (isShiftedMask_64(Val)) { in isRunOfOnes64()
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/openbsd/gnu/llvm/llvm/include/llvm/Support/ |
H A D | MathExtras.h | 318 constexpr inline bool isShiftedMask_64(uint64_t Value) { in isShiftedMask_64() function 387 inline bool isShiftedMask_64(uint64_t Value, unsigned &MaskIdx, in isShiftedMask_64() function 389 if (!isShiftedMask_64(Value)) in isShiftedMask_64()
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 1345 !isShiftedMask_64(CN->getZExtValue(), SMIdx, SMLen)) in performANDCombine() 1413 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine() 1457 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine() 1460 isShiftedMask_64(CN1->getZExtValue(), MaskIdx1, MaskLen1) && in performORCombine() 1479 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine() 1484 isShiftedMask_64(CN1->getZExtValue(), MaskIdx1, MaskLen1) && in performORCombine() 1502 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine() 1525 isShiftedMask_64(CN0->getZExtValue(), MaskIdx0, MaskLen0) && in performORCombine() 1544 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine() 1568 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 239 if (isShiftedMask_64(Imm)) { in processLogicalImmediate() 245 if (!isShiftedMask_64(~Imm)) in processLogicalImmediate()
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/openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 728 if (ShAmt <= 32 && isShiftedMask_64(Mask)) { in Select() 757 if (isShiftedMask_64(Mask) && N0.hasOneUse()) { in Select() 945 if (LeftShift && isShiftedMask_64(C1)) { in Select() 975 if (!LeftShift && isShiftedMask_64(C1)) { in Select() 1013 if (LeftShift && isShiftedMask_64(C1)) { in Select() 2188 if (isShiftedMask_64(Mask)) { in selectSHXADDOp() 2224 if (isShiftedMask_64(Mask)) { in selectSHXADDOp() 2278 if (isShiftedMask_64(Mask)) { in selectSHXADD_UWOp()
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H A D | RISCVTargetTransformInfo.cpp | 89 if (isShiftedMask_64(Mask)) { in canUseShiftPair()
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H A D | RISCVInstrInfoZb.td | 248 if (!isShiftedMask_64(Imm))
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H A D | RISCVInstrInfo.td | 483 return !isInt<32>(Imm) && isUInt<32>(Imm) && isShiftedMask_64(Imm) &&
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/openbsd/gnu/llvm/llvm/lib/Target/VE/ |
H A D | VE.h | 433 return (Val & (UINT64_C(1) << 63)) && isShiftedMask_64(Val); in isMImmVal()
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 303 (isShiftedMask_64(Imm.getZExtValue()) || in getIntImmCostInst() 304 isShiftedMask_64(~Imm.getZExtValue()))) in getIntImmCostInst()
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/openbsd/gnu/llvm/llvm/include/llvm/ADT/ |
H A D | APInt.h | 500 return isShiftedMask_64(U.VAL); in isShiftedMask() 512 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 1724 if (isShiftedMask_64(Mask, LSB, Length)) { in isRxSBGMask() 1732 if (isShiftedMask_64(Mask ^ allOnes(BitSize), LSB, Length)) { in isRxSBGMask()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 2725 if (!isShiftedMask_64(NonZeroBits)) in isBitfieldPositioningOp() 2747 assert(isShiftedMask_64(NonZeroBits) && "Caller guaranteed"); in isBitfieldPositioningOpFromAnd() 2869 assert(isShiftedMask_64(NonZeroBits) && "Caller guaranteed"); in isBitfieldPositioningOpFromShl() 2900 return isShiftedMask_64(Mask); in isShiftedMask() 3008 isShiftedMask_64(AndImm)) { in isWorthFoldingIntoOrrWithShift()
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H A D | AArch64ISelLowering.cpp | 2013 if (isShiftedMask_64(NewImm) || isShiftedMask_64(~(NewImm | ~Mask))) in optimizeLogicalImm()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 784 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) in performANDCombine() 866 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0)) in performORCombine() 874 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1)) in performORCombine() 1128 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) in performSHLCombine()
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2151 if (!isShiftedMask_64(Mask)) return true; in foldMaskedShiftToBEXTR() 5649 if (CmpVT == MVT::i64 && !isInt<8>(Mask) && isShiftedMask_64(Mask) && in Select()
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/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 3473 } else if (isShiftedMask_64(MaskVal)) { in tryBFE()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 3099 if (!MaskVal || !isShiftedMask_64(*MaskVal)) in select()
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 9676 (Bits == 8 || Bits == 16) && isShiftedMask_64(Mask) && !(Mask & 1)) { in performAndCombine()
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