Searched refs:lvds (Results 1 – 9 of 9) sorted by relevance
1227 ATOM_LVDS_INFO_V12 *lvds; in get_embedded_panel_info_v1_2() local1235 lvds = in get_embedded_panel_info_v1_2()1238 if (!lvds) in get_embedded_panel_info_v1_2()1252 le16_to_cpu(lvds->sLCDTiming.usHActive); in get_embedded_panel_info_v1_2()1298 info->ss_id = lvds->ucSS_Id; in get_embedded_panel_info_v1_2()1317 & lvds->ucLCDPanel_SpecialHandlingCap) in get_embedded_panel_info_v1_2()1346 ATOM_LCD_INFO_V13 *lvds; in get_embedded_panel_info_v1_3() local1356 if (!lvds) in get_embedded_panel_info_v1_3()1379 le16_to_cpu(lvds->sLCDTiming.usVActive); in get_embedded_panel_info_v1_3()1416 info->ss_id = lvds->ucSS_Id; in get_embedded_panel_info_v1_3()[all …]
1432 struct lcd_info_v2_1 *lvds; in get_embedded_panel_info_v2_1() local1440 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); in get_embedded_panel_info_v2_1()1442 if (!lvds) in get_embedded_panel_info_v2_1()1446 if (!((lvds->table_header.format_revision == 2) in get_embedded_panel_info_v2_1()1447 && (lvds->table_header.content_revision >= 1))) in get_embedded_panel_info_v2_1()1453 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()1474 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; in get_embedded_panel_info_v2_1()1475 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; in get_embedded_panel_info_v2_1()1488 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo in get_embedded_panel_info_v2_1()1492 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo in get_embedded_panel_info_v2_1()[all …]
1119 if (!lvds) in radeon_legacy_get_lvds_info_from_regs()1175 return lvds; in radeon_legacy_get_lvds_info_from_regs()1194 if (!lvds) in radeon_combios_get_lvds_info()1271 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in radeon_combios_get_lvds_info()1273 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in radeon_combios_get_lvds_info()1275 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in radeon_combios_get_lvds_info()1278 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in radeon_combios_get_lvds_info()1280 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + in radeon_combios_get_lvds_info()1282 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + in radeon_combios_get_lvds_info()1297 if (lvds) in radeon_combios_get_lvds_info()[all …]
74 if (lvds->bl_dev) in radeon_legacy_lvds_update()79 if (lvds->bl_dev) in radeon_legacy_lvds_update()154 lvds->dpms_mode = mode; in radeon_legacy_lvds_dpms()157 lvds->dpms_mode = mode; in radeon_legacy_lvds_dpms()211 if (lvds) { in radeon_legacy_lvds_mode_set()446 lvds->bl_dev = bd; in radeon_legacy_backlight_init()449 lvds->bl_dev = bd; in radeon_legacy_backlight_init()477 bd = lvds->bl_dev; in radeon_legacy_backlight_exit()478 lvds->bl_dev = NULL; in radeon_legacy_backlight_exit()481 bd = lvds->bl_dev; in radeon_legacy_backlight_exit()[all …]
1637 lvds = in radeon_atombios_get_lvds_info()1640 if (!lvds) in radeon_atombios_get_lvds_info()1649 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()1651 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()1653 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in radeon_atombios_get_lvds_info()1655 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in radeon_atombios_get_lvds_info()1657 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + in radeon_atombios_get_lvds_info()1659 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + in radeon_atombios_get_lvds_info()1688 lvds->linkb = true; in radeon_atombios_get_lvds_info()1690 lvds->linkb = false; in radeon_atombios_get_lvds_info()[all …]
799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; in radeon_set_pll() local800 if (lvds) { in radeon_set_pll()801 if (lvds->use_bios_dividers) { in radeon_set_pll()802 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()803 pll_fb_post_div = (lvds->panel_fb_divider | in radeon_set_pll()804 (lvds->panel_post_divider << 16)); in radeon_set_pll()
1982 lvds = in amdgpu_atombios_encoder_get_lcd_info()1985 if (!lvds) in amdgpu_atombios_encoder_get_lcd_info()1994 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()1996 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()1998 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in amdgpu_atombios_encoder_get_lcd_info()2000 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()2002 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()2004 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + in amdgpu_atombios_encoder_get_lcd_info()2033 lvds->linkb = true; in amdgpu_atombios_encoder_get_lcd_info()2035 lvds->linkb = false; in amdgpu_atombios_encoder_get_lcd_info()[all …]
844 u32 lvds; in intel_lvds_init() local865 lvds = intel_de_read(i915, lvds_reg); in intel_lvds_init()868 if ((lvds & LVDS_DETECTED) == 0) in intel_lvds_init()874 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()936 lvds_encoder->init_lvds_val = lvds; in intel_lvds_init()1000 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; in intel_lvds_init()
3894 u32 lvds = intel_de_read(dev_priv, LVDS); in i9xx_crtc_clock_get() local3899 if (lvds & LVDS_CLKB_POWER_UP) in i9xx_crtc_clock_get()