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Searched refs:mmDP0_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dce100/
H A Ddce100_resource.c87 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC macro
/openbsd/sys/dev/pci/drm/amd/display/dc/dce112/
H A Ddce112_resource.c86 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC macro
/openbsd/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_resource.c92 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5562 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_3_offset.h5048 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_1_offset.h8018 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_1_0_offset.h8447 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_1_0_offset.h9951 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_2_offset.h9630 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_0_0_offset.h11044 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_0_offset.h10766 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h4557 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc macro
H A Ddce_11_2_d.h5789 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc macro
H A Ddce_12_0_offset.h10298 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro