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Searched refs:mmDP1_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dce100/
H A Ddce100_resource.c88 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC macro
/openbsd/sys/dev/pci/drm/amd/display/dc/dce112/
H A Ddce112_resource.c87 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC macro
/openbsd/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_resource.c93 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5882 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_3_offset.h5391 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_1_offset.h8358 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_1_0_offset.h8757 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_1_0_offset.h10281 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_2_offset.h9973 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_0_0_offset.h11372 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_0_offset.h11109 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h4558 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc macro
H A Ddce_11_2_d.h5790 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc macro
H A Ddce_12_0_offset.h10582 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … macro