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Searched refs:mmUVD_LMI_SWAP_CNTL (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h51 #define mmUVD_LMI_SWAP_CNTL 0x3D6D macro
H A Duvd_4_2_d.h51 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_3_1_d.h53 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_5_0_d.h57 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_6_0_d.h73 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_7_0_offset.h162 #define mmUVD_LMI_SWAP_CNTL macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h342 #define mmUVD_LMI_SWAP_CNTL macro
H A Dvcn_2_0_0_offset.h574 #define mmUVD_LMI_SWAP_CNTL macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_uvd_v4_2.c309 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v4_2_start()
H A Damdgpu_uvd_v3_1.c351 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v3_1_start()
H A Duvd_v5_0.c360 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v5_0_start()
H A Dvcn_v1_0.c829 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in vcn_v1_0_start_spg_mode()
1014 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
H A Duvd_v6_0.c774 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v6_0_start()
H A Duvd_v7_0.c1016 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v7_0_start()
H A Dvcn_v2_0.c1016 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in vcn_v2_0_start()