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Searched refs:mmUVD_SEMA_TIMEOUT_STATUS (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h80 #define mmUVD_SEMA_TIMEOUT_STATUS 0x3DB0 macro
H A Duvd_4_2_d.h77 #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 macro
H A Duvd_3_1_d.h79 #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 macro
H A Duvd_5_0_d.h83 #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 macro
H A Duvd_6_0_d.h99 #define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 macro
H A Duvd_7_0_offset.h210 #define mmUVD_SEMA_TIMEOUT_STATUS … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h396 #define mmUVD_SEMA_TIMEOUT_STATUS … macro
H A Dvcn_2_5_offset.h813 #define mmUVD_SEMA_TIMEOUT_STATUS … macro
H A Dvcn_2_0_0_offset.h700 #define mmUVD_SEMA_TIMEOUT_STATUS … macro
H A Dvcn_3_0_0_offset.h1199 #define mmUVD_SEMA_TIMEOUT_STATUS … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_uvd_v4_2.c189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
H A Damdgpu_uvd_v3_1.c675 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v3_1_hw_init()
H A Duvd_v5_0.c186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
H A Duvd_v6_0.c498 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
H A Duvd_v7_0.c568 mmUVD_SEMA_TIMEOUT_STATUS), 0)); in uvd_v7_0_hw_init()