| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 173 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
175 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
207 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn303_fpu_update_bw_bounding_box()
208 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn303_fpu_update_bw_bounding_box()
338 if (dcn3_03_soc.num_chans <= 4) { in dcn303_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 175 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
178 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
211 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn302_fpu_update_bw_bounding_box()
212 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn302_fpu_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 149 .num_chans = 8,
168 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans * in get_optimal_ntuple()
174 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans * in get_optimal_ntuple()
177 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans * in get_optimal_ntuple()
192 memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans * in calculate_net_bw_in_kbytes_sec()
583 bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans * in dcn321_get_optimal_dcfclk_fclk_for_uclk()
585 bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans * in dcn321_get_optimal_dcfclk_fclk_for_uclk()
676 if (dc->ctx->dc_bios->vram_info.num_chans) { in dcn321_update_bw_bounding_box_fpu()
677 dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn321_update_bw_bounding_box_fpu()
679 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); in dcn321_update_bw_bounding_box_fpu()
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| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 69 uint32_t num_chans; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn10/ |
| H A D | dcn10_fpu.c | 120 .num_chans = 2,
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 295 .num_chans = 4,
597 dcn3_1_soc.num_chans = bw_params->num_channels; in dcn31_update_bw_bounding_box()
671 dcn3_15_soc.num_chans = bw_params->num_channels; in dcn315_update_bw_bounding_box()
736 dcn3_16_soc.num_chans = bw_params->num_channels; in dcn316_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 202 dcn3_14_soc.num_chans = bw_params->num_channels; in dcn314_update_bw_bounding_box_fpu()
204 ASSERT(dcn3_14_soc.num_chans); in dcn314_update_bw_bounding_box_fpu()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 202 .num_chans = 4,
338 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 160 .num_chans = 24,
442 dcn3_2_soc.num_chans * in calculate_net_bw_in_kbytes_sec()
471 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * in get_optimal_ntuple()
477 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * in get_optimal_ntuple()
480 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * in get_optimal_ntuple()
2286 bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * in dcn32_get_optimal_dcfclk_fclk_for_uclk()
2288 bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * in dcn32_get_optimal_dcfclk_fclk_for_uclk()
2764 if (dc->ctx->dc_bios->vram_info.num_chans) { in dcn32_update_bw_bounding_box_fpu()
2765 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn32_update_bw_bounding_box_fpu()
2767 dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); in dcn32_update_bw_bounding_box_fpu()
[all …]
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| H A D | display_mode_vba_util_32.c | 3291 double IdealDRAMBandwidth = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes; in dml32_get_return_bw_mbps()
3334 DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes in dml32_get_return_bw_mbps_vm_only()
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| /openbsd/sys/dev/pci/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 187 unsigned int num_chans; member
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 570 dc->dml.soc.num_chans <= 4 && in dcn30_fpu_calculate_wm_and_dlg()
623 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
625 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans * in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 231 unsigned int num_chans; member
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| H A D | display_mode_vba.c | 311 mode_lib->vba.NumberOfChannels = soc->num_chans; in fetch_socbb_params()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource.c | 2154 dc, dc->ctx->dc_bios->vram_info.num_chans) * in dcn32_resource_construct()
2709 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) in dcn32_calc_num_avail_chans_for_mall() argument
2750 return (num_chans == gc_11_0_0_max_chans) ? in dcn32_calc_num_avail_chans_for_mall()
2753 return (num_chans == gc_11_0_2_max_chans) ? in dcn32_calc_num_avail_chans_for_mall()
2756 return (num_chans == gc_11_0_3_max_chans) ? in dcn32_calc_num_avail_chans_for_mall()
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| H A D | dcn32_hwseq.c | 965 …cs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpi… in dcn32_init_hw()
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| H A D | dcn32_resource.h | 166 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans);
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 2107 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn30_update_bw_bounding_box()
2108 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn30_update_bw_bounding_box()
2287 …_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; in dcn30_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 318 .num_chans = 16,
429 .num_chans = 8,
540 .num_chans = 16,
754 .num_chans = 4,
2411 dcn2_1_soc.num_chans = bw_params->num_channels; in dcn21_update_bw_bounding_box()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/bios/ |
| H A D | bios_parser2.c | 2352 info->num_chans = info_v23->vram_module[0].channel_num; in get_vram_info_v23()
2371 info->num_chans = info_v24->vram_module[0].channel_num; in get_vram_info_v24()
2390 info->num_chans = info_v25->vram_module[0].channel_num; in get_vram_info_v25()
2409 info->num_chans = info_v30->channel_num; in get_vram_info_v30()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_resource.c | 226 .num_chans = 16,
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_resource.c | 1223 …_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; in dcn302_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_resource.c | 1147 dc->ctx->dc_bios->vram_info.num_chans * in dcn303_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn321/ |
| H A D | dcn321_resource.c | 1702 dc, dc->ctx->dc_bios->vram_info.num_chans) * in dcn321_resource_construct()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 1712 dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels; in dcn_bw_sync_calcs_and_dml()
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