Searched refs:pwr_state (Results 1 – 12 of 12) sorted by relevance
93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state()101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()162 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_update_clocks()167 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in rn_update_clocks()170 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in rn_update_clocks()451 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in rn_init_clocks()
166 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn31_update_clocks()176 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn31_update_clocks()193 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn31_update_clocks()197 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn31_update_clocks()305 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in dcn31_init_clocks()638 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn31_set_low_power_state()649 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn31_set_low_power_state()
116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in vg_update_clocks()128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks()133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in vg_update_clocks()138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks()383 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in vg_init_clocks()
162 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn316_update_clocks()172 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn316_update_clocks()182 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn316_update_clocks()186 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn316_update_clocks()
153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn315_update_clocks()163 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn315_update_clocks()172 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn315_update_clocks()176 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn315_update_clocks()
505 __field(int, pwr_state)523 __entry->pwr_state = clk->pwr_state;548 __entry->pwr_state,
193 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn314_update_clocks()203 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn314_update_clocks()220 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn314_update_clocks()225 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn314_update_clocks()
77 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; in amdgpu_dpm_set_powergating_by_smu()79 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()105 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
354 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; member
540 enum dcn_pwr_state pwr_state; member
1204 uint8_t pwr_state; member
3662 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); in amdgpu_device_init()