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Searched refs:pwr_state (Results 1 – 12 of 12) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state()
101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()
154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()
162 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_update_clocks()
167 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in rn_update_clocks()
170 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in rn_update_clocks()
451 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in rn_init_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c166 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn31_update_clocks()
176 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn31_update_clocks()
193 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn31_update_clocks()
197 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn31_update_clocks()
305 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in dcn31_init_clocks()
638 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn31_set_low_power_state()
649 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn31_set_low_power_state()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in vg_update_clocks()
128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks()
133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in vg_update_clocks()
138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks()
383 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in vg_init_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c162 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn316_update_clocks()
172 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn316_update_clocks()
182 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn316_update_clocks()
186 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn316_update_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn315_update_clocks()
163 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn315_update_clocks()
172 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn315_update_clocks()
176 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn315_update_clocks()
/openbsd/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_trace.h505 __field(int, pwr_state)
523 __entry->pwr_state = clk->pwr_state;
548 __entry->pwr_state,
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c193 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn314_update_clocks()
203 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn314_update_clocks()
220 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn314_update_clocks()
225 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn314_update_clocks()
/openbsd/sys/dev/pci/drm/amd/pm/
H A Damdgpu_dpm.c77 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; in amdgpu_dpm_set_powergating_by_smu()
79 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()
105 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
/openbsd/sys/dev/pci/drm/amd/pm/inc/
H A Damdgpu_dpm.h354 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; member
/openbsd/sys/dev/pci/drm/amd/display/dc/
H A Ddc.h540 enum dcn_pwr_state pwr_state; member
/openbsd/sys/dev/ic/
H A Dr92creg.h1204 uint8_t pwr_state; member
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_device.c3662 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); in amdgpu_device_init()