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Searched refs:regATC_L2_CACHE_4K_DSM_CNTL (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h2560 #define regATC_L2_CACHE_4K_DSM_CNTL … macro
H A Dmmhub_1_7_offset.h4356 #define regATC_L2_CACHE_4K_DSM_CNTL … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c1442 { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_CNTL) },
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h6622 #define regATC_L2_CACHE_4K_DSM_CNTL … macro
H A Dgc_9_4_3_offset.h1462 #define regATC_L2_CACHE_4K_DSM_CNTL … macro