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Searched refs:regCP_HQD_PQ_RPTR (Results 1 – 7 of 7) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dmes_v11_0.c1134 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); in mes_v11_0_kiq_dequeue()
H A Dgfx_v9_4_3.c1571 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); in gfx_v9_4_3_xcc_mqd_init()
1631 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, in gfx_v9_4_3_xcc_kiq_init_register()
1745 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); in gfx_v9_4_3_xcc_q_fini_register()
H A Dgfx_v11_0.c3845 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
3905 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h713 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_9_4_3_offset.h3302 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_11_0_0_offset.h4620 #define regCP_HQD_PQ_RPTR … macro
H A Dgc_11_0_3_offset.h4844 #define regCP_HQD_PQ_RPTR … macro