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Searched refs:ring_size (Results 1 – 25 of 104) sorted by relevance

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/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_ih.c44 unsigned ring_size, bool use_bus_addr) in amdgpu_ih_ring_init() argument
52 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
53 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
54 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
55 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
75 ih->ring_size + 8, in amdgpu_ih_ring_init()
77 ih->ring_size + 8, flags, 0); in amdgpu_ih_ring_init()
86 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
87 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; in amdgpu_ih_ring_init()
88 ih->rptr_addr = dma_addr + ih->ring_size + 4; in amdgpu_ih_ring_init()
[all …]
H A Dnavi10_ih.c53 if (adev->irq.ih.ring_size) { in navi10_ih_init_register_offset()
66 if (adev->irq.ih1.ring_size) { in navi10_ih_init_register_offset()
77 if (adev->irq.ih2.ring_size) { in navi10_ih_init_register_offset()
203 if (ih[i]->ring_size) { in navi10_ih_toggle_interrupts()
215 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl()
353 if (ih[i]->ring_size) { in navi10_ih_irq_init()
373 if (adev->irq.ih_soft.ring_size) in navi10_ih_irq_init()
474 if ((v < ih->ring_size) && (v != ih->rptr)) in navi10_ih_irq_rearm()
581 adev->irq.ih1.ring_size = 0; in navi10_ih_sw_init()
582 adev->irq.ih2.ring_size = 0; in navi10_ih_sw_init()
H A Dih_v6_1.c52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
65 if (adev->irq.ih1.ring_size) { in ih_v6_1_init_register_offset()
177 if (ih[i]->ring_size) { in ih_v6_1_toggle_interrupts()
189 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v6_1_rb_cntl()
319 if (ih[i]->ring_size) { in ih_v6_1_irq_init()
358 if (adev->irq.ih_soft.ring_size) in ih_v6_1_irq_init()
451 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_1_irq_rearm()
553 adev->irq.ih1.ring_size = 0; in ih_v6_1_sw_init()
554 adev->irq.ih2.ring_size = 0; in ih_v6_1_sw_init()
H A Dih_v6_0.c52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
65 if (adev->irq.ih1.ring_size) { in ih_v6_0_init_register_offset()
205 if (ih[i]->ring_size) { in ih_v6_0_toggle_interrupts()
217 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v6_0_rb_cntl()
347 if (ih[i]->ring_size) { in ih_v6_0_irq_init()
386 if (adev->irq.ih_soft.ring_size) in ih_v6_0_irq_init()
478 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_0_irq_rearm()
580 adev->irq.ih1.ring_size = 0; in ih_v6_0_sw_init()
581 adev->irq.ih2.ring_size = 0; in ih_v6_0_sw_init()
H A Dvega10_ih.c51 if (adev->irq.ih.ring_size) { in vega10_ih_init_register_offset()
64 if (adev->irq.ih1.ring_size) { in vega10_ih_init_register_offset()
75 if (adev->irq.ih2.ring_size) { in vega10_ih_init_register_offset()
148 if (ih[i]->ring_size) { in vega10_ih_toggle_interrupts()
160 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl()
285 if (ih[i]->ring_size) { in vega10_ih_irq_init()
303 if (adev->irq.ih_soft.ring_size) in vega10_ih_irq_init()
404 if ((v < ih->ring_size) && (v != ih->rptr)) in vega10_ih_irq_rearm()
H A Dvega20_ih.c59 if (adev->irq.ih.ring_size) { in vega20_ih_init_register_offset()
72 if (adev->irq.ih1.ring_size) { in vega20_ih_init_register_offset()
83 if (adev->irq.ih2.ring_size) { in vega20_ih_init_register_offset()
184 if (ih[i]->ring_size) { in vega20_ih_toggle_interrupts()
196 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega20_ih_rb_cntl()
345 if (ih[i]->ring_size) { in vega20_ih_irq_init()
378 if (adev->irq.ih_soft.ring_size) in vega20_ih_irq_init()
480 if ((v < ih->ring_size) && (v != ih->rptr)) in vega20_ih_irq_rearm()
H A Damdgpu_ring.c321 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); in amdgpu_ring_init()
323 ring->buf_mask = (ring->ring_size / 4) - 1; in amdgpu_ring_init()
331 BUG_ON(ring->ring_size > PAGE_SIZE*4); in amdgpu_ring_init()
340 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE, in amdgpu_ring_init()
497 if (*pos >= (ring->ring_size + 12)) in amdgpu_debugfs_ring_read()
608 ring->ring_size + 12); in amdgpu_debugfs_ring_init()
661 prop->queue_size = ring->ring_size; in amdgpu_ring_to_mqd_prop()
H A Damdgpu_ih.h52 unsigned ring_size; member
102 unsigned ring_size, bool use_bus_addr);
H A Damdgpu_ring_mux.c66 amdgpu_ring_alloc(real_ring, (ring->ring_size >> 2) + end - start); in amdgpu_ring_mux_copy_pkt_from_sw_ring()
68 (ring->ring_size >> 2) - start); in amdgpu_ring_mux_copy_pkt_from_sw_ring()
317 readp += mux->real_ring->ring_size >> 2; in amdgpu_ring_mux_get_rptr()
318 end += mux->real_ring->ring_size >> 2; in amdgpu_ring_mux_get_rptr()
H A Dpsp_v10_0.c84 psp_ring_reg = ring->ring_size; in psp_v10_0_ring_create()
H A Dvcn_v2_0.c887 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
1059 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1088 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_start()
1097 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_start()
1240 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1960 ring->ring_size / 4); in vcn_v2_0_start_sriov()
1974 tmp = order_base_2(ring->ring_size); in vcn_v2_0_start_sriov()
H A Dpsp_v11_0_8.c109 psp_ring_reg = ring->ring_size; in psp_v11_0_8_ring_create()
H A Dvcn_v2_5.c919 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
1111 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1140 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_start()
1149 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_start()
1316 ring->ring_size / 4); in vcn_v2_5_sriov_start()
1330 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1489 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1499 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
H A Damdgpu_vce_v2_0.c248 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); in vce_v2_0_start()
255 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); in vce_v2_0_start()
H A Dvcn_v3_0.c1044 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start_dpg_mode()
1231 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start()
1265 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_start()
1274 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_start()
1403 ring->ring_size / 4); in vcn_v3_0_start_sriov()
1416 tmp = order_base_2(ring->ring_size); in vcn_v3_0_start_sriov()
1639 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
1649 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
H A Dvce_v4_0.c239 ring->ring_size / 4); in vce_v4_0_sriov_start()
347 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4); in vce_v4_0_start()
355 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4); in vce_v4_0_start()
363 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4); in vce_v4_0_start()
H A Dvce_v3_0.c285 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); in vce_v3_0_start()
292 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); in vce_v3_0_start()
299 WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4); in vce_v3_0_start()
/openbsd/sys/dev/pci/drm/radeon/
H A Dradeon_ring.c86 ring->ring_free_dw = rptr + (ring->ring_size / 4); in radeon_ring_free_size()
91 ring->ring_free_dw = ring->ring_size / 4; in radeon_ring_free_size()
112 if (ndw > (ring->ring_size / 4)) in radeon_ring_alloc()
314 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
381 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, in radeon_ring_init() argument
386 ring->ring_size = ring_size; in radeon_ring_init()
392 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, in radeon_ring_init()
417 ring->ptr_mask = (ring->ring_size / 4) - 1; in radeon_ring_init()
418 ring->ring_free_dw = ring->ring_size / 4; in radeon_ring_init()
474 count = (ring->ring_size / 4) - ring->ring_free_dw; in radeon_debugfs_ring_info_show()
H A Dni.c1681 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
2034 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_uvd_start()
2042 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in cayman_uvd_resume()
2046 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2114 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_vce_start()
2115 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_vce_start()
2123 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in cayman_vce_resume()
2127 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2133 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2241 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
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H A Dvce_v1_0.c302 WREG32(VCE_RB_SIZE, ring->ring_size / 4); in vce_v1_0_start()
309 WREG32(VCE_RB_SIZE2, ring->ring_size / 4); in vce_v1_0_start()
H A Dr600.c2730 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2786 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2787 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
2788 ring->ring_size = ring_size; in r600_ring_init()
3084 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_uvd_start()
3471 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3472 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3473 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3474 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3484 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
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/openbsd/sys/dev/pci/
H A Dif_bnxt.c128 uint32_t ring_size; member
973 i = rx->rx_ag_ring.ring_size; in bnxt_queue_up()
978 i = rx->rx_ring.ring_size; in bnxt_queue_up()
1012 tx->tx_ring.ring_size); in bnxt_queue_down()
1016 rx->rx_ag_ring.ring_size); in bnxt_queue_down()
1020 rx->rx_ring.ring_size); in bnxt_queue_down()
1357 free += tx->tx_ring.ring_size; in bnxt_start()
1416 if (idx == tx->tx_ring.ring_size) in bnxt_start()
1468 if (idx == tx->tx_ring.ring_size) in bnxt_start()
2210 if (++p >= ring->ring_size) in bnxt_rx_fill_slots()
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/openbsd/sys/dev/pci/drm/i915/gvt/
H A Dcmd_parser.c488 unsigned long ring_size; member
738 s->ring_start, s->ring_start + s->ring_size, in parser_exec_state_dump()
815 if (s->ip_gma >= s->ring_start + s->ring_size) in ip_gma_advance()
816 s->ip_gma -= s->ring_size; in ip_gma_advance()
1259 s->ret_ip_gma_ring -= s->ring_size; in cmd_handler_mi_batch_buffer_end()
2899 s.ring_size = ring_size; in scan_wa_ctx()
2911 wa_ctx->indirect_ctx.guest_gma, ring_size); in scan_wa_ctx()
3131 s.ring_size = engine->context_size - start; in intel_gvt_update_reg_whitelist()
3133 s.ring_tail = s.ring_size; in intel_gvt_update_reg_whitelist()
3142 ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size); in intel_gvt_update_reg_whitelist()
[all …]
/openbsd/sys/dev/pci/drm/include/uapi/linux/
H A Dkfd_ioctl.h67 __u32 ring_size; /* to KFD */ member
90 __u32 ring_size; /* to KFD */ member
975 __u32 ring_size; member
/openbsd/sys/dev/pci/drm/i915/gt/
H A Dintel_context_types.h112 u32 ring_size; member

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