1 /* $OpenBSD: if_rtw_pci.c,v 1.22 2024/05/24 06:02:56 jsg Exp $ */
2 /* $NetBSD: if_rtw_pci.c,v 1.1 2004/09/26 02:33:36 dyoung Exp $ */
3
4 /*-
5 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center; Charles M. Hannum; and David Young.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * PCI bus front-end for the Realtek RTL8180L 802.11 MAC/BBP chip.
36 *
37 * Derived from the ADMtek ADM8211 PCI bus front-end.
38 *
39 * Derived from the ``Tulip'' PCI bus front-end.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/device.h>
45
46 #include <net/if.h>
47 #include <net/if_media.h>
48 #include <netinet/in.h>
49 #include <netinet/if_ether.h>
50
51 #include <net80211/ieee80211_radiotap.h>
52 #include <net80211/ieee80211_var.h>
53
54 #include <machine/bus.h>
55 #include <machine/intr.h>
56
57 #include <dev/ic/rtwreg.h>
58 #include <dev/ic/rtwvar.h>
59
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcidevs.h>
63
64 int rtw_pci_enable(struct rtw_softc *);
65 void rtw_pci_disable(struct rtw_softc *);
66 int rtw_pci_detach(struct device *, int);
67
68 /*
69 * PCI configuration space registers used by the RTL8180L.
70 */
71 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */
72 #define RTW_PCI_MMBA 0x14 /* memory mapped base */
73
74 struct rtw_pci_softc {
75 struct rtw_softc psc_rtw; /* real RTL8180L softc */
76
77 pci_intr_handle_t psc_ih; /* interrupt handle */
78 void *psc_intrcookie;
79
80 pci_chipset_tag_t psc_pc; /* our PCI chipset */
81 pcitag_t psc_pcitag; /* our PCI tag */
82 bus_size_t psc_mapsize;
83 };
84
85 int rtw_pci_match(struct device *, void *, void *);
86 void rtw_pci_attach(struct device *, struct device *, void *);
87
88 const struct cfattach rtw_pci_ca = {
89 sizeof (struct rtw_pci_softc), rtw_pci_match, rtw_pci_attach,
90 rtw_pci_detach, rtw_activate
91 };
92
93 const struct pci_matchid rtw_pci_products[] = {
94 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180 },
95 #ifdef RTW_DEBUG
96 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8185 },
97 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D7010 },
98 #endif
99 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6001 },
100 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6020V3 },
101 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610 },
102 };
103
104 int
rtw_pci_match(struct device * parent,void * match,void * aux)105 rtw_pci_match(struct device *parent, void *match, void *aux)
106 {
107 return (pci_matchbyid((struct pci_attach_args *)aux, rtw_pci_products,
108 nitems(rtw_pci_products)));
109 }
110
111 int
rtw_pci_enable(struct rtw_softc * sc)112 rtw_pci_enable(struct rtw_softc *sc)
113 {
114 struct rtw_pci_softc *psc = (void *)sc;
115
116 /* Establish the interrupt. */
117 psc->psc_intrcookie = pci_intr_establish(psc->psc_pc, psc->psc_ih,
118 IPL_NET, rtw_intr, sc, sc->sc_dev.dv_xname);
119 if (psc->psc_intrcookie == NULL) {
120 printf("%s: unable to establish interrupt\n",
121 sc->sc_dev.dv_xname);
122 return (1);
123 }
124
125 return (0);
126 }
127
128 void
rtw_pci_disable(struct rtw_softc * sc)129 rtw_pci_disable(struct rtw_softc *sc)
130 {
131 struct rtw_pci_softc *psc = (void *)sc;
132
133 /* Unhook the interrupt handler. */
134 pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie);
135 psc->psc_intrcookie = NULL;
136 }
137
138 void
rtw_pci_attach(struct device * parent,struct device * self,void * aux)139 rtw_pci_attach(struct device *parent, struct device *self, void *aux)
140 {
141 struct rtw_pci_softc *psc = (void *) self;
142 struct rtw_softc *sc = &psc->psc_rtw;
143 struct rtw_regs *regs = &sc->sc_regs;
144 struct pci_attach_args *pa = aux;
145 pci_chipset_tag_t pc = pa->pa_pc;
146 const char *intrstr = NULL;
147 bus_space_tag_t iot, memt;
148 bus_space_handle_t ioh, memh;
149 bus_size_t iosize, memsize;
150 int ioh_valid, memh_valid;
151
152 psc->psc_pc = pa->pa_pc;
153 psc->psc_pcitag = pa->pa_tag;
154
155 /*
156 * No power management hooks.
157 * XXX Maybe we should add some!
158 */
159 sc->sc_flags |= RTW_F_ENABLED;
160
161 /*
162 * Get revision info, and set some chip-specific variables.
163 */
164 sc->sc_rev = PCI_REVISION(pa->pa_class);
165
166 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
167
168 /*
169 * Map the device.
170 */
171 ioh_valid = (pci_mapreg_map(pa, RTW_PCI_IOBA,
172 PCI_MAPREG_TYPE_IO, 0,
173 &iot, &ioh, NULL, &iosize, 0) == 0);
174 memh_valid = (pci_mapreg_map(pa, RTW_PCI_MMBA,
175 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
176 &memt, &memh, NULL, &memsize, 0) == 0);
177
178 if (memh_valid) {
179 regs->r_bt = memt;
180 regs->r_bh = memh;
181 psc->psc_mapsize = memsize;
182 } else if (ioh_valid) {
183 regs->r_bt = iot;
184 regs->r_bh = ioh;
185 psc->psc_mapsize = iosize;
186 } else {
187 printf(": unable to map device registers\n");
188 return;
189 }
190
191 sc->sc_dmat = pa->pa_dmat;
192
193 /*
194 * Map and establish our interrupt.
195 */
196 if (pci_intr_map(pa, &psc->psc_ih)) {
197 printf(": unable to map interrupt\n");
198 return;
199 }
200 intrstr = pci_intr_string(pc, psc->psc_ih);
201 psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET,
202 rtw_intr, sc, sc->sc_dev.dv_xname);
203 if (psc->psc_intrcookie == NULL) {
204 printf(": unable to establish interrupt");
205 if (intrstr != NULL)
206 printf(" at %s", intrstr);
207 printf("\n");
208 return;
209 }
210
211 printf(": %s\n", intrstr);
212
213 sc->sc_enable = rtw_pci_enable;
214 sc->sc_disable = rtw_pci_disable;
215
216 /*
217 * Finish off the attach.
218 */
219 rtw_attach(sc);
220 }
221
222 int
rtw_pci_detach(struct device * self,int flags)223 rtw_pci_detach(struct device *self, int flags)
224 {
225 struct rtw_pci_softc *psc = (void *)self;
226 struct rtw_softc *sc = &psc->psc_rtw;
227 struct rtw_regs *regs = &sc->sc_regs;
228 int rv;
229
230 rv = rtw_detach(sc);
231 if (rv)
232 return (rv);
233 if (psc->psc_intrcookie != NULL)
234 pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie);
235 bus_space_unmap(regs->r_bt, regs->r_bh, psc->psc_mapsize);
236
237 return (0);
238 }
239