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Searched refs:rxdctl (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/
H A Dif_ixv.c947 uint32_t reg, rxdctl, bufsz, psrtype; in ixv_initialize_receive_units() local
973 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)); in ixv_initialize_receive_units()
974 rxdctl &= ~IXGBE_RXDCTL_ENABLE; in ixv_initialize_receive_units()
975 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl); in ixv_initialize_receive_units()
1007 rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME; in ixv_initialize_receive_units()
1008 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl); in ixv_initialize_receive_units()
H A Dif_igc.c2308 uint32_t rxdctl; in igc_initialize_receive_unit() local
2323 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); in igc_initialize_receive_unit()
2324 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; in igc_initialize_receive_unit()
2325 rxdctl &= 0xFFF00000; in igc_initialize_receive_unit()
2326 rxdctl |= IGC_RX_PTHRESH; in igc_initialize_receive_unit()
2327 rxdctl |= IGC_RX_HTHRESH << 8; in igc_initialize_receive_unit()
2328 rxdctl |= IGC_RX_WTHRESH << 16; in igc_initialize_receive_unit()
2329 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); in igc_initialize_receive_unit()
H A Dif_ngbe.c755 uint32_t rxdctl; in ngbe_stop() local
771 rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i)); in ngbe_stop()
772 } while (--wait_loop && (rxdctl & NGBE_PX_RR_CFG_RR_EN)); in ngbe_stop()
1573 uint32_t bufsz, mhadd, rxctrl, rxdctl, srrctl; in ngbe_initialize_receive_unit() local
1608 rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i)); in ngbe_initialize_receive_unit()
1609 } while (--wait_loop && (rxdctl & NGBE_PX_RR_CFG_RR_EN)); in ngbe_initialize_receive_unit()
1621 rxdctl = NGBE_READ_REG(hw, NGBE_PX_RR_CFG(i)); in ngbe_initialize_receive_unit()
1622 rxdctl |= in ngbe_initialize_receive_unit()
1624 rxdctl |= 0x1 << NGBE_PX_RR_CFG_RR_THER_SHIFT; in ngbe_initialize_receive_unit()
1625 NGBE_WRITE_REG(hw, NGBE_PX_RR_CFG(i), rxdctl); in ngbe_initialize_receive_unit()
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H A Dif_ix.c735 uint32_t k, txdctl, rxdctl, rxctrl, mhadd, itr; in ixgbe_init() local
808 rxdctl = IXGBE_READ_REG(&sc->hw, IXGBE_RXDCTL(i)); in ixgbe_init()
815 rxdctl &= ~0x3FFFFF; in ixgbe_init()
816 rxdctl |= 0x080420; in ixgbe_init()
818 rxdctl |= IXGBE_RXDCTL_ENABLE; in ixgbe_init()
819 IXGBE_WRITE_REG(&sc->hw, IXGBE_RXDCTL(i), rxdctl); in ixgbe_init()
H A Dif_em.c3512 uint32_t rctl, rxdctl; in em_flush_rx_ring() local
3520 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL(que->me)); in em_flush_rx_ring()
3522 rxdctl &= 0xffffc000; in em_flush_rx_ring()
3527 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); in em_flush_rx_ring()
3528 EM_WRITE_REG(&sc->hw, E1000_RXDCTL(que->me), rxdctl); in em_flush_rx_ring()