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Searched refs:snps (Results 1 – 6 of 6) sorted by relevance

/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_ddi_buf_trans.c1016 { .snps = { 62, 0, 0 } }, /* preset 0 */
1017 { .snps = { 55, 0, 7 } }, /* preset 1 */
1018 { .snps = { 50, 0, 12 } }, /* preset 2 */
1019 { .snps = { 44, 0, 18 } }, /* preset 3 */
1020 { .snps = { 35, 0, 21 } }, /* preset 4 */
1021 { .snps = { 59, 3, 0 } }, /* preset 5 */
1022 { .snps = { 53, 3, 6 } }, /* preset 6 */
1023 { .snps = { 48, 3, 11 } }, /* preset 7 */
1024 { .snps = { 42, 5, 15 } }, /* preset 8 */
1025 { .snps = { 37, 5, 20 } }, /* preset 9 */
[all …]
H A Dintel_ddi_buf_trans.h60 struct dg2_snps_phy_buf_trans snps; member
H A Dintel_display_core.h494 } snps; member
H A Dintel_snps_phy.c43 i915->display.snps.phy_failed_calibration |= BIT(phy); in intel_snps_phy_wait_for_calibration()
77 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); in intel_snps_phy_set_signal_levels()
78 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); in intel_snps_phy_set_signal_levels()
79 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); in intel_snps_phy_set_signal_levels()
H A Dintel_cx0_phy.c395 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), in intel_cx0_phy_set_signal_levels()
399 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), in intel_cx0_phy_set_signal_levels()
403 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), in intel_cx0_phy_set_signal_levels()
H A Dintel_ddi.c4789 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()