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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
52 def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2),
56 def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2),
78 def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2),
82 def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2),
86 def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2),
90 def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2),
100 def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2),
118 def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2),
1997 def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
28 (MI HvxVR:$src1, HvxVR:$src2)>;
32 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
33 (MI HvxWR:$src1, HvxWR:$src2)>;
35 (MI HvxWR:$src1, HvxWR:$src2)>;
86 (MI HvxQR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td119 (MI HvxWR:$src1, IntRegs:$src2)>;
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
135 (MI HvxWR:$src1, HvxVR:$src2)>;
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
143 (MI HvxWR:$src1, HvxWR:$src2)>;
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
151 (MI HvxVR:$src1, HvxVR:$src2)>;
163 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
[all …]
H A DHexagonIntrinsics.td135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
289 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
299 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
301 (SUB_64_VAL u3_64_ImmPred:$src2))>,
323 (MI HvxVR:$src1, HvxVR:$src2,
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td93 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
97 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
101 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
105 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
141 u8imm:$src2, u8imm:$src3),
143 timm:$src2, timm:$src3)]>;
145 u8imm:$src2, u8imm:$src3),
149 u8imm:$src2, u8imm:$src3),
153 u8imm:$src2, u8imm:$src3),
165 "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrSSE.td28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
51 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
58 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
81 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 def : InstAlias<OpcodeStr#".s\t{$src2, $dst|$dst, $src2}",
5702 "vptest\t{$src2, $src1|$src1, $src2}",
5724 "ptest\t{$src2, $src1|$src1, $src2}",
5728 "ptest\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrFMA.td42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
83 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td36 "shl{b}\t{$src2, $dst|$dst, $src2}",
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
49 "shl{q}\t{$src2, $dst|$dst, $src2}",
141 "shr{b}\t{$src2, $dst|$dst, $src2}",
144 "shr{w}\t{$src2, $dst|$dst, $src2}",
148 "shr{l}\t{$src2, $dst|$dst, $src2}",
152 "shr{q}\t{$src2, $dst|$dst, $src2}",
245 "sar{b}\t{$src2, $dst|$dst, $src2}",
248 "sar{w}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
21 "loadiwkey\t{$src2, $src1|$src1, $src2}",
22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
41 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
43 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
47 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
49 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
53 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
55 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8XS,
59 "aesdec256kl\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrCMovSetCC.td21 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
27 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
33 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
42 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
47 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
48 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
52 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrCompiler.td716 "{$src2, $dst|$dst, $src2}"),
723 "{$src2, $dst|$dst, $src2}"),
731 "{$src2, $dst|$dst, $src2}"),
739 "{$src2, $dst|$dst, $src2}"),
748 "{$src2, $dst|$dst, $src2}"),
756 "{$src2, $dst|$dst, $src2}"),
764 "{$src2, $dst|$dst, $src2}"),
772 "{$src2, $dst|$dst, $src2}"),
779 "{$src2, $dst|$dst, $src2}"),
787 "{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrArithmetic.td155 "imul{w}\t{$src2, $dst|$dst, $src2}",
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
175 "imul{w}\t{$src2, $dst|$dst, $src2}",
181 "imul{l}\t{$src2, $dst|$dst, $src2}",
187 "imul{q}\t{$src2, $dst|$dst, $src2}",
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
679 mnemonic, "{$src2, $dst|$dst, $src2}", []>,
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
[all …]
H A DX86InstrMMX.td39 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
57 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
62 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
67 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
527 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrAVX512.td1782 OpcodeStr, "$src3, $src2", "$src2, $src3",
1904 OpcodeStr, "$src3, $src2", "$src2, $src3",
4932 "$src2, $src1", "$src1, $src2",
5994 "$src2, $src1", "$src1, $src2",
5999 "$src2, $src1", "$src1, $src2",
6016 "$src2, $src1", "$src1, $src2",
6021 "$src2, $src1", "$src1, $src2",
6633 "$src2, $src1", "$src1, $src2",
6639 "$src2, $src1", "$src1, $src2",
12481 "$src3, $src2", "$src2, $src3",
[all …]
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
27 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
28 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
30 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
H A DX86InstrVecCompiler.td417 (ANDPSrm VR128:$src1, f128mem:$src2)>;
420 (ANDPSrr VR128:$src1, VR128:$src2)>;
423 (ORPSrm VR128:$src1, f128mem:$src2)>;
426 (ORPSrr VR128:$src1, VR128:$src2)>;
429 (XORPSrm VR128:$src1, f128mem:$src2)>;
432 (XORPSrr VR128:$src1, VR128:$src2)>;
438 (VANDPSrm VR128:$src1, f128mem:$src2)>;
441 (VANDPSrr VR128:$src1, VR128:$src2)>;
444 (VORPSrm VR128:$src1, f128mem:$src2)>;
447 (VORPSrr VR128:$src1, VR128:$src2)>;
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/cpu/
H A Dm32r.cpu2073 (set new-src2 (add WI src2 (const WI 4)))
2075 (set src2 new-src2))
2079 (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2081 (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2092 (set new-src2 (add src2 (const 2)))
2093 (set src2 new-src2))
2108 (set new-src2 (add src2 (const 1)))
2109 (set src2 new-src2))
2124 ; (set src2 (sub src2 (const 4)))
2127 (set new-src2 (sub src2 (const 4)))
[all …]
/openbsd/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/execute/
H A Dstring-opt-7.c18 const char *src2; in main() local
44 dst2 = dst; src2 = src; in main()
45 if (strncpy (++dst2, ++src2, 0) != dst+1 || strcmp (dst2, "") in main()
46 || dst2 != dst+1 || src2 != src+1) in main()
50 dst2 = dst; src2 = src; in main()
51 if (strncpy (++dst2+5, ++src2+5, 0) != dst+6 || strcmp (dst2+5, "") in main()
52 || dst2 != dst+1 || src2 != src+1) in main()
/openbsd/gnu/llvm/clang/lib/Headers/
H A Damxintrin.h255 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbssd_internal() argument
256 return __builtin_ia32_tdpbssd_internal(m, n, k, dst, src1, src2); in _tile_dpbssd_internal()
262 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbsud_internal() argument
263 return __builtin_ia32_tdpbsud_internal(m, n, k, dst, src1, src2); in _tile_dpbsud_internal()
269 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbusd_internal() argument
270 return __builtin_ia32_tdpbusd_internal(m, n, k, dst, src1, src2); in _tile_dpbusd_internal()
276 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbuud_internal() argument
277 return __builtin_ia32_tdpbuud_internal(m, n, k, dst, src1, src2); in _tile_dpbuud_internal()
291 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbf16ps_internal() argument
292 return __builtin_ia32_tdpbf16ps_internal(m, n, k, dst, src1, src2); in _tile_dpbf16ps_internal()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td225 // src1 = Denominator, src2 = Numerator).
231 // Denominator, src2 = Numerator).
327 SDTCisSameAs<4, 2>, // f32 src2
394 [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
395 (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
398 [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
434 [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
454 [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
458 [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
474 [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td619 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
621 def insertll : PatFrag<(ops node:$src1, node:$src2),
658 def z_sadd : PatFrags<(ops node:$src1, node:$src2),
661 def z_uadd : PatFrags<(ops node:$src1, node:$src2),
664 def z_ssub : PatFrags<(ops node:$src1, node:$src2),
667 def z_usub : PatFrags<(ops node:$src1, node:$src2),
672 def andc : PatFrag<(ops node:$src1, node:$src2),
674 def orc : PatFrag<(ops node:$src1, node:$src2),
676 def nand : PatFrag<(ops node:$src1, node:$src2),
678 def nor : PatFrag<(ops node:$src1, node:$src2),
[all …]
/openbsd/gnu/llvm/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX906.rst66 …id_gfx906_src_1>`::ref:`f16x2<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
67 …id_gfx906_src_4>`::ref:`i16x2<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
68 …id_gfx906_src_4>`::ref:`u16x2<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
69 …id_gfx906_src_1>`::ref:`i8x4<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
70 …id_gfx906_src_1>`::ref:`u8x4<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
71 …id_gfx906_src_1>`::ref:`i4x8<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
72 …id_gfx906_src_1>`::ref:`u4x8<amdgpu_synid_gfx906_type_deviation>`, :ref:`src2<amdgpu_synid_gfx906…
73 …amdgpu_synid_gfx906_m>`::ref:`fx<amdgpu_synid_gfx906_fx_operand>`, :ref:`src2<amdgpu_synid_gfx906…
74 …amdgpu_synid_gfx906_m>`::ref:`fx<amdgpu_synid_gfx906_fx_operand>`, :ref:`src2<amdgpu_synid_gfx906…
75 …amdgpu_synid_gfx906_m>`::ref:`fx<amdgpu_synid_gfx906_fx_operand>`, :ref:`src2<amdgpu_synid_gfx906…
/openbsd/gnu/llvm/llvm/include/llvm/Target/
H A DGenericOpcodes.td99 let InOperandList = (ins unknown:$src2);
247 let InOperandList = (ins type0:$src1, type0:$src2);
255 let InOperandList = (ins type0:$src1, type0:$src2);
263 let InOperandList = (ins type0:$src1, type0:$src2);
271 let InOperandList = (ins type0:$src1, type0:$src2);
279 let InOperandList = (ins type0:$src1, type0:$src2);
287 let InOperandList = (ins type0:$src1, type0:$src2);
295 let InOperandList = (ins type0:$src1, type0:$src2);
303 let InOperandList = (ins type0:$src1, type0:$src2);
311 let InOperandList = (ins type0:$src1, type0:$src2);
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td449 let Constraints = "$src2 = $rd" in {
993 def : Pat<(addc GR16:$src, GR16:$src2),
997 def : Pat<(addc GR16:$src, imm:$src2),
1004 def : Pat<(addc GR8:$src, GR8:$src2),
1005 (ADD8rr GR8:$src, GR8:$src2)>;
1008 def : Pat<(addc GR8:$src, imm:$src2),
1009 (ADD8ri GR8:$src, imm:$src2)>;
1015 def : Pat<(subc GR16:$src, GR16:$src2),
1019 def : Pat<(subc GR16:$src, imm:$src2),
1026 def : Pat<(subc GR8:$src, GR8:$src2),
[all …]

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