Searched refs:uimm8 (Results 1 – 13 of 13) sorted by relevance
/openbsd/gnu/llvm/llvm/docs/AMDGPU/ |
H A D | gfx7_soffset_67d76d.rst | 17 * If offset is specified as an :ref:`uimm8<amdgpu_synid_uimm8>`, it supplies an 8-bit unsigned dwor… 21 …ch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`uimm8<amdgpu_synid_uimm8…
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/openbsd/gnu/usr.bin/binutils-2.17/cpu/ |
H A D | sh64-compact.cpu | 364 "and #$uimm8, r0" 365 (+ (f-op8 #xc9) uimm8) 366 (set r0 (and r0 (zext DI uimm8)))) 1383 "or #$uimm8, r0" 1384 (+ (f-op8 #xcb) uimm8) 1698 "trapa #$uimm8" 1699 (+ (f-op8 #xc3) uimm8) 1710 "tst #$uimm8, r0" 1711 (+ (f-op8 #xc8) uimm8) 1730 "xor #$uimm8, r0" [all …]
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H A D | m32r.cpu | 473 (dnf f-uimm8 "uimm8" () 8 8) 668 (dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8) 2376 ; PSW &= ~((unsigned char) uimm8 | 0x000ff00) 2379 "clrpsw $uimm8" 2380 (+ OP1_7 (f-r1 2) uimm8) 2383 (or USI (inv BI uimm8) (const #xff00)))) 2387 ; PSW |= (unsigned char) uimm8 2390 "setpsw $uimm8" 2391 (+ OP1_7 (f-r1 1) uimm8) 2392 (set USI (reg h-cr 0) uimm8)
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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrInfo16Instr.td | 123 (ins mGPR:$rx, uimm8:$imm8), "rsubi16 $rd, $rx, $imm8", []>; 168 def MOVI16 : I16_Z_8<0b110, (ins uimm8:$imm8), "movi16\t$rz, $imm8"> { 172 let Pattern = [(set mGPR:$rz, uimm8:$imm8)]; 685 def : CompressPat<(MOVI32 mGPR:$rd, uimm8:$imm), 686 (MOVI16 mGPR:$rd, uimm8:$imm)>;
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H A D | CSKYInstrInfo.td | 316 def uimm8 : uimm<8> {
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/ |
H A D | LoongArchInstrInfo.td | 206 def uimm8 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isUInt<8>(Imm);}]> { 1696 (ins GPR:$rj, uimm8:$imm8), "lddir", "$rd, $rj, $imm8">; 1697 def LDPTE : FmtLDPTE<(outs), (ins GPR:$rj, uimm8:$seq), "ldpte", "$rj, $seq">; 1733 (LDDIR GPR:$rj, uimm8:$imm8)>; 1735 (LDPTE GPR:$rj, uimm8:$imm8)>;
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MicroMipsDSPInstrInfo.td | 358 dag InOperandList = (ins uimm8:$imm);
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H A D | MicroMipsInstrInfo.td | 158 let MIOperandInfo = (ops ptr_sp_rc, uimm8);
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H A D | MipsDSPInstrInfo.td | 863 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
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H A D | MipsInstrInfo.td | 1784 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel),
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H A D | MipsMSAInstrInfo.td | 1272 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
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/openbsd/gnu/llvm/llvm/docs/ |
H A D | AMDGPUOperandSyntax.rst | 719 uimm8 section in Operands
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/openbsd/gnu/usr.bin/binutils-2.17/opcodes/ |
H A D | bfin-dis.c | 383 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf) macro
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