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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp863 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
864 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
865 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
3140 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3148 { ISD::SELECT, MVT::v8i64, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3391 { ISD::BITREVERSE, MVT::v8i64, { 3 } }, in getIntrinsicInstrCost()
3395 { ISD::BSWAP, MVT::v8i64, { 1 } }, in getIntrinsicInstrCost()
3459 { ISD::BITREVERSE, MVT::v8i64, { 36 } }, in getIntrinsicInstrCost()
3463 { ISD::BSWAP, MVT::v8i64, { 4 } }, in getIntrinsicInstrCost()
5244 {ISD::SMIN, MVT::v8i64, 1}, in getMinMaxCost()
[all …]
H A DX86CallingConv.td127 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
157 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
202 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
255 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
314 CCIfType<[v16f32, v8f64, v16i32, v8i64],
582 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
602 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
721 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
780 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
796 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
[all …]
H A DX86InstrVecCompiler.td93 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
105 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
143 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, sub_xmm>;
150 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, sub_ymm>;
159 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, sub_xmm>;
166 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, sub_ymm>;
H A DX86InstrAVX512.td3709 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 immAllZerosV),
4794 def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))),
6324 (EXTRACT_SUBREG (v8i64
6330 (EXTRACT_SUBREG (v8i64
6336 (EXTRACT_SUBREG (v8i64
6342 (EXTRACT_SUBREG (v8i64
6460 (EXTRACT_SUBREG (v8i64
6466 (EXTRACT_SUBREG (v8i64
6486 (EXTRACT_SUBREG (v8i64
6491 (EXTRACT_SUBREG (v8i64
[all …]
H A DX86InstrFragmentsSIMD.td852 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
927 (v8i64 (alignedload node:$ptr))>;
976 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
H A DX86RegisterInfo.td589 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64],
593 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
H A DX86ISelLowering.cpp1811 for (auto VT : { MVT::v16i32, MVT::v8i64 }) { in X86TargetLowering()
1853 for (auto VT : { MVT::v16i32, MVT::v8i64} ) { in X86TargetLowering()
1859 for (auto VT : { MVT::v16i32, MVT::v8i64 }) in X86TargetLowering()
11084 case MVT::v8i64: in createVariablePermute()
13136 case MVT::v8i64: in lowerShuffleAsBlend()
19043 MVT::v8i64, in lowerV8I64Shuffle()
19384 case MVT::v8i64: in lower512BitShuffle()
21351 if (VT == MVT::v8i64 && Subtarget.hasDQI()) in isLegalConversion()
33616 if (VT == MVT::v16i32 || VT == MVT::v8i64) { in ReplaceNodeResults()
57471 case MVT::v8i64: in getRegForInlineAsmConstraint()
[all …]
H A DX86ISelDAGToDAG.cpp4520 VPTESTM_CASE(v8i64, QZ##SUFFIX) in getVPTESTMOpc()
5979 else if (IndexVT == MVT::v8i64 && NumElts == 8 && EltSize == 32) in Select()
5985 else if (IndexVT == MVT::v8i64 && NumElts == 8 && EltSize == 64) in Select()
6073 else if (IndexVT == MVT::v8i64 && NumElts == 8 && EltSize == 32) in Select()
6079 else if (IndexVT == MVT::v8i64 && NumElts == 8 && EltSize == 64) in Select()
H A DX86FastISel.cpp450 case MVT::v8i64: in X86FastEmitLoad()
621 case MVT::v8i64: in X86FastEmitStore()
H A DX86.td184 // FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp476 {Intrinsic::bswap, MVT::v8i64, 31},
502 {Intrinsic::vp_bswap, MVT::v8i64, 31},
540 {Intrinsic::vp_fshl, MVT::v8i64, 7},
578 {Intrinsic::vp_fshr, MVT::v8i64, 7},
613 {Intrinsic::bitreverse, MVT::v8i64, 52},
648 {Intrinsic::vp_bitreverse, MVT::v8i64, 52},
683 {Intrinsic::ctpop, MVT::v8i64, 21},
718 {Intrinsic::vp_ctpop, MVT::v8i64, 21},
756 {Intrinsic::vp_ctlz, MVT::v8i64, 35},
794 {Intrinsic::vp_cttz, MVT::v8i64, 25},
/openbsd/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h134 v8i64 = 79, // 8 x i64 enumerator
452 SimpleTy == MVT::v8i64); in is512BitVector()
635 case v8i64: in getVectorElementType()
817 case v8i64: in getVectorMinNumElements()
1070 case v8i64: in getSizeInBits()
1343 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1835 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 4}, // 3 x uzp1 + xtn in getCastInstrCost()
1837 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 3}, // 3 x uzp1 in getCastInstrCost()
1838 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 2}, // 2 x uzp1 in getCastInstrCost()
1873 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
1874 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
1875 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
1876 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
2467 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp667 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
668 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
669 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
670 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
997 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
H A DARMRegisterInfo.td592 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
599 def MQQQQPR : RegisterClass<"ARM", [v8i64], 256, (trunc QQQQPR, 5)>;
H A DARMISelDAGToDAG.cpp2375 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST()
2504 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td900 defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>;
953 defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>;
986 defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>;
H A DSIInstructions.td1613 def : BitConvert <v8i64, v8f64, VReg_512>;
1614 def : BitConvert <v8f64, v8i64, VReg_512>;
1615 def : BitConvert <v8i64, v16i32, VReg_512>;
1617 def : BitConvert <v16i32, v8i64, VReg_512>;
1619 def : BitConvert <v8i64, v16f32, VReg_512>;
1621 def : BitConvert <v16f32, v8i64, VReg_512>;
H A DAMDGPUISelLowering.cpp129 setOperationAction(ISD::LOAD, MVT::v8i64, Promote); in AMDGPUTargetLowering()
130 AddPromotedToType(ISD::LOAD, MVT::v8i64, MVT::v16i32); in AMDGPUTargetLowering()
255 setOperationAction(ISD::STORE, MVT::v8i64, Promote); in AMDGPUTargetLowering()
256 AddPromotedToType(ISD::STORE, MVT::v8i64, MVT::v16i32); in AMDGPUTargetLowering()
373 MVT::v3i64, MVT::v4f64, MVT::v4i64, MVT::v8f64, MVT::v8i64, in AMDGPUTargetLowering()
H A DSIISelLowering.cpp138 addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass); in SITargetLowering()
206 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand); in SITargetLowering()
207 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Expand); in SITargetLowering()
208 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Expand); in SITargetLowering()
263 MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64, MVT::v8i16, in SITargetLowering()
339 for (MVT Vec64 : { MVT::v8i64, MVT::v8f64 }) { in SITargetLowering()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.td107 def v8i64 : ValueType<512, 79>; // 8 x i64 vector value
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenTarget.cpp145 case MVT::v8i64: return "MVT::v8i64"; in getEnumName()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DValueTypes.cpp337 case MVT::v8i64: in getTypeForEVT()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp115 case MVT::v8i64: in INITIALIZE_PASS()
505 case MVT::v8i64: in SelectIndexedStore()
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1402 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) { in lowerLoadI1()
1521 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) { in lowerStoreI1()

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