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Searched refs:vm_manager (Results 1 – 25 of 62) sorted by relevance

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/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_ids.c206 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
223 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
234 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
235 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
281 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_reserved()
297 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
368 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
551 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_reset_all()
571 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_mgr_init()
578 id_mgr->num_ids = adev->vm_manager.first_kfd_vmid; in amdgpu_vmid_mgr_init()
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H A Damdgpu_vm.c444 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
450 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
1591 if (lpfn >= adev->vm_manager.max_pfn) in amdgpu_vm_verify_parameters()
2170 adev->vm_manager.block_size = in amdgpu_vm_adjust_size()
2175 adev->vm_manager.block_size = 9; in amdgpu_vm_adjust_size()
2186 adev->vm_manager.block_size, in amdgpu_vm_adjust_size()
2187 adev->vm_manager.fragment_size); in amdgpu_vm_adjust_size()
2503 adev->vm_manager.fence_context = in amdgpu_vm_manager_init()
2506 adev->vm_manager.seqno[i] = 0; in amdgpu_vm_manager_init()
2521 adev->vm_manager.vm_update_mode = in amdgpu_vm_manager_init()
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H A Damdgpu_vm_pt.c57 adev->vm_manager.block_size; in amdgpu_vm_pt_level_shift()
79 shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_pt_num_entries()
80 if (level == adev->vm_manager.root_level) in amdgpu_vm_pt_num_entries()
82 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_pt_num_entries()
104 shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_pt_num_ats_entries()
120 if (level <= adev->vm_manager.root_level) in amdgpu_vm_pt_entries_mask()
179 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
378 unsigned int level = adev->vm_manager.root_level; in amdgpu_vm_pt_clear()
746 enum amdgpu_vm_level root = adev->vm_manager.root_level; in amdgpu_vm_pt_is_root_clean()
781 level += params->adev->vm_manager.root_level; in amdgpu_vm_pde_update()
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H A Dgfxhub_v3_0_3.c173 + adev->vm_manager.vram_base_offset; in gfxhub_v3_0_3_init_system_aperture_regs()
306 adev->vm_manager.num_level); in gfxhub_v3_0_3_setup_vmid_config()
323 adev->vm_manager.block_size - 9); in gfxhub_v3_0_3_setup_vmid_config()
336 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
339 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
H A Dgmc_v6_0.c438 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
495 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
519 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
540 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
867 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
875 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
877 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
H A Damdgpu_vm.h55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
399 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
400 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
401 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
H A Dmmhub_v3_0_2.c185 adev->vm_manager.vram_base_offset; in mmhub_v3_0_2_init_system_aperture_regs()
322 adev->vm_manager.num_level); in mmhub_v3_0_2_setup_vmid_config()
340 adev->vm_manager.block_size - 9); in mmhub_v3_0_2_setup_vmid_config()
353 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
356 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
H A Dgfxhub_v3_0.c168 + adev->vm_manager.vram_base_offset; in gfxhub_v3_0_init_system_aperture_regs()
301 adev->vm_manager.num_level); in gfxhub_v3_0_setup_vmid_config()
318 adev->vm_manager.block_size - 9); in gfxhub_v3_0_setup_vmid_config()
331 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
334 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
H A Dmmhub_v3_0_1.c192 adev->vm_manager.vram_base_offset; in mmhub_v3_0_1_init_system_aperture_regs()
317 adev->vm_manager.num_level); in mmhub_v3_0_1_setup_vmid_config()
335 adev->vm_manager.block_size - 9); in mmhub_v3_0_1_setup_vmid_config()
348 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
351 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
H A Dmmhub_v3_0.c193 adev->vm_manager.vram_base_offset; in mmhub_v3_0_init_system_aperture_regs()
330 adev->vm_manager.num_level); in mmhub_v3_0_setup_vmid_config()
348 adev->vm_manager.block_size - 9); in mmhub_v3_0_setup_vmid_config()
361 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
364 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
H A Dgfxhub_v2_0.c293 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
310 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
323 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
326 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
H A Dgfxhub_v1_0.c257 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
258 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
303 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
306 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
H A Dgmc_v7_0.c571 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
640 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
669 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
687 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1047 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1055 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1057 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
H A Dmmhub_v2_0.c373 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
391 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
404 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
407 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c291 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
309 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
H A Dmmhub_v1_0.c239 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
240 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
281 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
284 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
H A Dgfxhub_v1_2.c324 num_level = adev->vm_manager.num_level; in gfxhub_v1_2_xcc_setup_vmid_config()
325 block_size = adev->vm_manager.block_size; in gfxhub_v1_2_xcc_setup_vmid_config()
377 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_2_xcc_setup_vmid_config()
381 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_2_xcc_setup_vmid_config()
H A Dgmc_v8_0.c786 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
856 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
900 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
925 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1160 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1168 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1170 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
H A Damdgpu_csa.c31 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
H A Dmmhub_v1_8.c335 num_level = adev->vm_manager.num_level; in mmhub_v1_8_setup_vmid_config()
336 block_size = adev->vm_manager.block_size; in mmhub_v1_8_setup_vmid_config()
386 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_8_setup_vmid_config()
390 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_8_setup_vmid_config()
H A Dgfxhub_v2_1.c302 adev->vm_manager.num_level); in gfxhub_v2_1_setup_vmid_config()
319 adev->vm_manager.block_size - 9); in gfxhub_v2_1_setup_vmid_config()
332 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
335 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
H A Dgmc_v11_0.c501 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v11_0_get_vm_pde()
688 adev->vm_manager.vram_base_offset = 0; in gmc_v11_0_vram_gtt_location()
690 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
854 adev->vm_manager.first_kfd_vmid = 8; in gmc_v11_0_sw_init()
H A Damdgpu_amdkfd.c156 ((1 << adev->vm_manager.first_kfd_vmid) - 1), in amdgpu_amdkfd_device_init()
159 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
727 return vmid >= adev->vm_manager.first_kfd_vmid; in amdgpu_amdkfd_is_kfd_vmid()
H A Dgmc_v9_0.c1689 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
1692 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
2085 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2107 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2116 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2126 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2205 adev->vm_manager.first_kfd_vmid = in gmc_v9_0_sw_init()
/openbsd/sys/dev/pci/drm/radeon/
H A Dradeon_vm.c89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
196 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
216 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
275 radeon_fence_unref(&rdev->vm_manager.active[vm_id]); in radeon_vm_fence()
467 if (last_pfn >= rdev->vm_manager.max_pfn) { in radeon_vm_bo_set_addr()
469 last_pfn, rdev->vm_manager.max_pfn); in radeon_vm_bo_set_addr()
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