1 /* CPU data for xc16x.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996-2005 Free Software Foundation, Inc.
6
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "sysdep.h"
26 #include <stdio.h>
27 #include <stdarg.h>
28 #include "ansidecl.h"
29 #include "bfd.h"
30 #include "symcat.h"
31 #include "xc16x-desc.h"
32 #include "xc16x-opc.h"
33 #include "opintl.h"
34 #include "libiberty.h"
35 #include "xregex.h"
36
37 /* Attributes. */
38
39 static const CGEN_ATTR_ENTRY bool_attr[] =
40 {
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44 };
45
46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47 {
48 { "base", MACH_BASE },
49 { "xc16x", MACH_XC16X },
50 { "max", MACH_MAX },
51 { 0, 0 }
52 };
53
54 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
55 {
56 { "xc16x", ISA_XC16X },
57 { "max", ISA_MAX },
58 { 0, 0 }
59 };
60
61 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
62 {
63 { "NONE", PIPE_NONE },
64 { "OS", PIPE_OS },
65 { 0, 0 }
66 };
67
68 const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
69 {
70 { "MACH", & MACH_attr[0], & MACH_attr[0] },
71 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
72 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
73 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
74 { "RESERVED", &bool_attr[0], &bool_attr[0] },
75 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
76 { "SIGNED", &bool_attr[0], &bool_attr[0] },
77 { "RELOC", &bool_attr[0], &bool_attr[0] },
78 { 0, 0, 0 }
79 };
80
81 const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
82 {
83 { "MACH", & MACH_attr[0], & MACH_attr[0] },
84 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
85 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
86 { "PC", &bool_attr[0], &bool_attr[0] },
87 { "PROFILE", &bool_attr[0], &bool_attr[0] },
88 { 0, 0, 0 }
89 };
90
91 const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
92 {
93 { "MACH", & MACH_attr[0], & MACH_attr[0] },
94 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
95 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
96 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
97 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
98 { "SIGNED", &bool_attr[0], &bool_attr[0] },
99 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
100 { "RELAX", &bool_attr[0], &bool_attr[0] },
101 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
102 { "RELOC", &bool_attr[0], &bool_attr[0] },
103 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
104 { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
105 { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
106 { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
107 { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
108 { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
109 { 0, 0, 0 }
110 };
111
112 const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
113 {
114 { "MACH", & MACH_attr[0], & MACH_attr[0] },
115 { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
116 { "ALIAS", &bool_attr[0], &bool_attr[0] },
117 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
118 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
119 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
120 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
121 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
122 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
123 { "RELAXED", &bool_attr[0], &bool_attr[0] },
124 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
125 { "PBB", &bool_attr[0], &bool_attr[0] },
126 { 0, 0, 0 }
127 };
128
129 /* Instruction set variants. */
130
131 static const CGEN_ISA xc16x_cgen_isa_table[] = {
132 { "xc16x", 16, 32, 16, 32 },
133 { 0, 0, 0, 0, 0 }
134 };
135
136 /* Machine variants. */
137
138 static const CGEN_MACH xc16x_cgen_mach_table[] = {
139 { "xc16x", "xc16x", MACH_XC16X, 32 },
140 { 0, 0, 0, 0 }
141 };
142
143 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
144 {
145 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
146 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
147 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
148 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
149 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
150 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
151 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
152 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
153 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
154 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
155 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
156 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
157 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
158 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
159 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
160 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
161 };
162
163 CGEN_KEYWORD xc16x_cgen_opval_gr_names =
164 {
165 & xc16x_cgen_opval_gr_names_entries[0],
166 16,
167 0, 0, 0, 0, ""
168 };
169
170 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
171 {
172 { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
173 { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
174 { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
175 { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
176 { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
177 { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
178 { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
179 { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
180 };
181
182 CGEN_KEYWORD xc16x_cgen_opval_ext_names =
183 {
184 & xc16x_cgen_opval_ext_names_entries[0],
185 8,
186 0, 0, 0, 0, ""
187 };
188
189 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
190 {
191 { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
192 { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
193 { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
194 { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
195 { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
196 { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
197 { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
198 { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
199 { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
200 { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
201 { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
202 { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
203 { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
204 { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
205 { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
206 { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
207 { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
208 };
209
210 CGEN_KEYWORD xc16x_cgen_opval_psw_names =
211 {
212 & xc16x_cgen_opval_psw_names_entries[0],
213 17,
214 0, 0, 0, 0, ""
215 };
216
217 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
218 {
219 { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
220 { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
221 { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
222 { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
223 { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
224 { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
225 { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
226 { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
227 { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
228 { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
229 { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
230 { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
231 { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
232 { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
233 { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
234 { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
235 };
236
237 CGEN_KEYWORD xc16x_cgen_opval_grb_names =
238 {
239 & xc16x_cgen_opval_grb_names_entries[0],
240 16,
241 0, 0, 0, 0, ""
242 };
243
244 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
245 {
246 { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
247 { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
248 { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
249 { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
250 { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
251 { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
252 { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
253 { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
254 { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
255 { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
256 { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
257 { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
258 { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
259 { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
260 { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
261 { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
262 { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
263 { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
264 { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
265 { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
266 };
267
268 CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
269 {
270 & xc16x_cgen_opval_conditioncode_names_entries[0],
271 20,
272 0, 0, 0, 0, ""
273 };
274
275 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
276 {
277 { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
278 { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
279 { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
280 { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
281 { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
282 { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
283 { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
284 { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
285 { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
286 { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
287 { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
288 { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
289 { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
290 { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
291 { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
292 { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
293 { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
294 { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
295 { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
296 { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
297 { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
298 { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
299 { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
300 { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
301 };
302
303 CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
304 {
305 & xc16x_cgen_opval_extconditioncode_names_entries[0],
306 24,
307 0, 0, 0, 0, ""
308 };
309
310 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
311 {
312 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
313 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
314 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
315 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
316 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
317 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
318 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
319 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
320 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
321 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
322 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
323 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
324 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
325 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
326 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
327 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
328 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
329 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
330 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
331 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
332 { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
333 { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
334 { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
335 { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
336 { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
337 { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
338 { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
339 { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
340 { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
341 { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
342 { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
343 { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
344 { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
345 { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
346 { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
347 { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
348 };
349
350 CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
351 {
352 & xc16x_cgen_opval_grb8_names_entries[0],
353 36,
354 0, 0, 0, 0, ""
355 };
356
357 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
358 {
359 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
360 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
361 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
362 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
363 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
364 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
365 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
366 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
367 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
368 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
369 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
370 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
371 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
372 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
373 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
374 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
375 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
376 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
377 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
378 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
379 { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
380 { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
381 { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
382 { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
383 { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
384 { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
385 { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
386 { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
387 { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
388 { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
389 { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
390 { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
391 { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
392 { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
393 { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
394 { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
395 };
396
397 CGEN_KEYWORD xc16x_cgen_opval_r8_names =
398 {
399 & xc16x_cgen_opval_r8_names_entries[0],
400 36,
401 0, 0, 0, 0, ""
402 };
403
404 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
405 {
406 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
407 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
408 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
409 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
410 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
411 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
412 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
413 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
414 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
415 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
416 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
417 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
418 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
419 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
420 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
421 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
422 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
423 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
424 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
425 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
426 { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
427 { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
428 { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
429 { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
430 { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
431 { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
432 { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
433 { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
434 { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
435 { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
436 { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
437 { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
438 { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
439 { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
440 { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
441 { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
442 };
443
444 CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
445 {
446 & xc16x_cgen_opval_regmem8_names_entries[0],
447 36,
448 0, 0, 0, 0, ""
449 };
450
451 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
452 {
453 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
454 { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
455 { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
456 { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
457 { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
458 { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
459 { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
460 { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
461 { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
462 { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
463 { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
464 { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
465 { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
466 { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
467 { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
468 { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
469 };
470
471 CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
472 {
473 & xc16x_cgen_opval_regdiv8_names_entries[0],
474 16,
475 0, 0, 0, 0, ""
476 };
477
478 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
479 {
480 { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
481 { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
482 { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
483 { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
484 { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
485 { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
486 { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
487 { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
488 { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
489 { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
490 { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
491 { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
492 { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
493 { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
494 { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
495 { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
496 { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
497 { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
498 { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
499 { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
500 { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
501 { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
502 { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
503 { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
504 { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
505 { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
506 { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
507 { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
508 { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
509 { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
510 };
511
512 CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
513 {
514 & xc16x_cgen_opval_reg0_name_entries[0],
515 30,
516 0, 0, 0, 0, ""
517 };
518
519 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
520 {
521 { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
522 { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
523 { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
524 { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
525 { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
526 { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
527 { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
528 { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
529 { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
530 { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
531 { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
532 { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
533 { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
534 { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
535 };
536
537 CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
538 {
539 & xc16x_cgen_opval_reg0_name1_entries[0],
540 14,
541 0, 0, 0, 0, ""
542 };
543
544 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
545 {
546 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
547 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
548 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
549 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
550 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
551 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
552 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
553 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
554 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
555 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
556 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
557 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
558 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
559 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
560 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
561 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
562 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
563 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
564 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
565 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
566 { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
567 { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
568 { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
569 { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
570 { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
571 { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
572 { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
573 { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
574 { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
575 { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
576 { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
577 { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
578 { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
579 { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
580 { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
581 { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
582 };
583
584 CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
585 {
586 & xc16x_cgen_opval_regbmem8_names_entries[0],
587 36,
588 0, 0, 0, 0, ""
589 };
590
591 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
592 {
593 { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
594 { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
595 { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
596 { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
597 { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
598 { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
599 { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
600 { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
601 { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
602 { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
603 { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
604 { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
605 { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
606 { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
607 { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
608 { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
609 { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
610 { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
611 { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
612 { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
613 };
614
615 CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
616 {
617 & xc16x_cgen_opval_memgr8_names_entries[0],
618 20,
619 0, 0, 0, 0, ""
620 };
621
622
623 /* The hardware table. */
624
625 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
626 #define A(a) (1 << CGEN_HW_##a)
627 #else
628 #define A(a) (1 << CGEN_HW_/**/a)
629 #endif
630
631 const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
632 {
633 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
634 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
635 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
636 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
637 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
638 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
639 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
640 { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
641 { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
642 { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
643 { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
644 { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
645 { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
646 { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
647 { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
648 { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
649 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
650 { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
651 { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
652 { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
653 { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
654 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
655 { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
656 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
657 };
658
659 #undef A
660
661
662 /* The instruction field table. */
663
664 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
665 #define A(a) (1 << CGEN_IFLD_##a)
666 #else
667 #define A(a) (1 << CGEN_IFLD_/**/a)
668 #endif
669
670 const CGEN_IFLD xc16x_cgen_ifld_table[] =
671 {
672 { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
673 { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
674 { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
675 { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
676 { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
677 { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
678 { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
679 { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
680 { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
681 { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
682 { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
683 { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
684 { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
685 { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
686 { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
687 { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
688 { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
689 { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
690 { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
691 { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
692 { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
693 { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
694 { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
695 { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
696 { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
697 { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
698 { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
699 { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
700 { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
701 { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
702 { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
703 { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
704 { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } },
705 { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
706 { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
707 { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
708 { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
709 { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
710 { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
711 { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
712 { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
713 { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
714 { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
715 { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
716 { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
717 { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
718 { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
719 { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
720 { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
721 { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
722 { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
723 { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
724 { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
725 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
726 };
727
728 #undef A
729
730
731
732 /* multi ifield declarations */
733
734
735
736 /* multi ifield definitions */
737
738
739 /* The operand table. */
740
741 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
742 #define A(a) (1 << CGEN_OPERAND_##a)
743 #else
744 #define A(a) (1 << CGEN_OPERAND_/**/a)
745 #endif
746 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
747 #define OPERAND(op) XC16X_OPERAND_##op
748 #else
749 #define OPERAND(op) XC16X_OPERAND_/**/op
750 #endif
751
752 const CGEN_OPERAND xc16x_cgen_operand_table[] =
753 {
754 /* pc: program counter */
755 { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
756 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
757 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
758 /* sr: source register */
759 { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
760 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
761 { 0, { { { (1<<MACH_BASE), 0 } } } } },
762 /* dr: destination register */
763 { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
764 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
765 { 0, { { { (1<<MACH_BASE), 0 } } } } },
766 /* dri: destination register */
767 { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
768 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
769 { 0, { { { (1<<MACH_BASE), 0 } } } } },
770 /* srb: source register */
771 { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
772 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
773 { 0, { { { (1<<MACH_BASE), 0 } } } } },
774 /* drb: destination register */
775 { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
776 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
777 { 0, { { { (1<<MACH_BASE), 0 } } } } },
778 /* sr2: 2 bit source register */
779 { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
780 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
781 { 0, { { { (1<<MACH_BASE), 0 } } } } },
782 /* src1: source register 1 */
783 { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
784 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
785 { 0, { { { (1<<MACH_BASE), 0 } } } } },
786 /* src2: source register 2 */
787 { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
788 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
789 { 0, { { { (1<<MACH_BASE), 0 } } } } },
790 /* srdiv: source register 2 */
791 { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
792 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
793 { 0, { { { (1<<MACH_BASE), 0 } } } } },
794 /* RegNam: PSW bits */
795 { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
796 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
797 { 0, { { { (1<<MACH_BASE), 0 } } } } },
798 /* uimm2: 2 bit unsigned number */
799 { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
800 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
801 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
802 /* uimm3: 3 bit unsigned number */
803 { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
804 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
805 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
806 /* uimm4: 4 bit unsigned number */
807 { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
808 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
809 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
810 /* uimm7: 7 bit trap number */
811 { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
812 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
813 { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
814 /* uimm8: 8 bit unsigned immediate */
815 { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
816 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
817 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
818 /* uimm16: 16 bit unsigned immediate */
819 { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
820 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
821 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
822 /* upof16: 16 bit unsigned immediate */
823 { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
824 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
825 { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
826 /* reg8: 8 bit word register number */
827 { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
828 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
829 { 0, { { { (1<<MACH_BASE), 0 } } } } },
830 /* regmem8: 8 bit word register number */
831 { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
832 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
833 { 0, { { { (1<<MACH_BASE), 0 } } } } },
834 /* regbmem8: 8 bit byte register number */
835 { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
836 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
837 { 0, { { { (1<<MACH_BASE), 0 } } } } },
838 /* regoff8: 8 bit word register number */
839 { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
840 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
841 { 0, { { { (1<<MACH_BASE), 0 } } } } },
842 /* reghi8: 8 bit word register number */
843 { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
844 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
845 { 0, { { { (1<<MACH_BASE), 0 } } } } },
846 /* regb8: 8 bit byte register number */
847 { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
848 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
849 { 0, { { { (1<<MACH_BASE), 0 } } } } },
850 /* genreg: 8 bit word register number */
851 { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
852 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
853 { 0, { { { (1<<MACH_BASE), 0 } } } } },
854 /* seg: 8 bit segment number */
855 { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
856 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
857 { 0, { { { (1<<MACH_BASE), 0 } } } } },
858 /* seghi8: 8 bit hi segment number */
859 { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
860 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
861 { 0, { { { (1<<MACH_BASE), 0 } } } } },
862 /* caddr: 16 bit address offset */
863 { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
864 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
865 { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
866 /* rel: 8 bit signed relative offset */
867 { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
868 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
869 { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
870 /* relhi: hi 8 bit signed relative offset */
871 { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
872 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
873 { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
874 /* condbit: condition bit */
875 { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
876 { 0, { (const PTR) 0 } },
877 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
878 /* bit1: gap of 1 bit */
879 { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
880 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
881 { 0, { { { (1<<MACH_BASE), 0 } } } } },
882 /* bit2: gap of 2 bits */
883 { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
884 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
885 { 0, { { { (1<<MACH_BASE), 0 } } } } },
886 /* bit4: gap of 4 bits */
887 { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
888 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
889 { 0, { { { (1<<MACH_BASE), 0 } } } } },
890 /* lbit4: gap of 4 bits */
891 { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
892 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
893 { 0, { { { (1<<MACH_BASE), 0 } } } } },
894 /* lbit2: gap of 2 bits */
895 { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
896 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
897 { 0, { { { (1<<MACH_BASE), 0 } } } } },
898 /* bit8: gap of 8 bits */
899 { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
900 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
901 { 0, { { { (1<<MACH_BASE), 0 } } } } },
902 /* u4: gap of 4 bits */
903 { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
904 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
905 { 0, { { { (1<<MACH_BASE), 0 } } } } },
906 /* bitone: field of 1 bit */
907 { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
908 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
909 { 0, { { { (1<<MACH_BASE), 0 } } } } },
910 /* bit01: field of 1 bit */
911 { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
912 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
913 { 0, { { { (1<<MACH_BASE), 0 } } } } },
914 /* cond: condition code */
915 { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
916 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
917 { 0, { { { (1<<MACH_BASE), 0 } } } } },
918 /* icond: indirect condition code */
919 { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
920 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
921 { 0, { { { (1<<MACH_BASE), 0 } } } } },
922 /* extcond: extended condition code */
923 { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
924 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
925 { 0, { { { (1<<MACH_BASE), 0 } } } } },
926 /* memory: 16 bit memory */
927 { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
928 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
929 { 0, { { { (1<<MACH_BASE), 0 } } } } },
930 /* memgr8: 16 bit memory */
931 { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
932 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
933 { 0, { { { (1<<MACH_BASE), 0 } } } } },
934 /* cbit: carry bit */
935 { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
936 { 0, { (const PTR) 0 } },
937 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
938 /* qbit: bit addr */
939 { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
940 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
941 { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
942 /* qlobit: bit addr */
943 { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
944 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
945 { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
946 /* qhibit: bit addr */
947 { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
948 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
949 { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
950 /* mask8: 8 bit mask */
951 { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
952 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
953 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
954 /* masklo8: 8 bit mask */
955 { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
956 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
957 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
958 /* pagenum: 10 bit page number */
959 { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
960 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
961 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
962 /* data8: 8 bit data */
963 { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
964 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
965 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
966 /* datahi8: 8 bit data */
967 { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
968 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
969 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
970 /* sgtdisbit: segmentation enable bit */
971 { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
972 { 0, { (const PTR) 0 } },
973 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
974 /* upag16: 16 bit unsigned immediate */
975 { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
976 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
977 { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
978 /* useg8: 8 bit segment */
979 { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
980 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
981 { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
982 /* useg16: 16 bit address offset */
983 { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
984 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
985 { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
986 /* usof16: 16 bit address offset */
987 { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
988 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
989 { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
990 /* hash: # prefix */
991 { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
992 { 0, { (const PTR) 0 } },
993 { 0, { { { (1<<MACH_BASE), 0 } } } } },
994 /* dot: . prefix */
995 { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
996 { 0, { (const PTR) 0 } },
997 { 0, { { { (1<<MACH_BASE), 0 } } } } },
998 /* pof: pof: prefix */
999 { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
1000 { 0, { (const PTR) 0 } },
1001 { 0, { { { (1<<MACH_BASE), 0 } } } } },
1002 /* pag: pag: prefix */
1003 { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
1004 { 0, { (const PTR) 0 } },
1005 { 0, { { { (1<<MACH_BASE), 0 } } } } },
1006 /* sof: sof: prefix */
1007 { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
1008 { 0, { (const PTR) 0 } },
1009 { 0, { { { (1<<MACH_BASE), 0 } } } } },
1010 /* segm: seg: prefix */
1011 { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
1012 { 0, { (const PTR) 0 } },
1013 { 0, { { { (1<<MACH_BASE), 0 } } } } },
1014 /* sentinel */
1015 { 0, 0, 0, 0, 0,
1016 { 0, { (const PTR) 0 } },
1017 { 0, { { { (1<<MACH_BASE), 0 } } } } }
1018 };
1019
1020 #undef A
1021
1022
1023 /* The instruction table. */
1024
1025 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1026 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1027 #define A(a) (1 << CGEN_INSN_##a)
1028 #else
1029 #define A(a) (1 << CGEN_INSN_/**/a)
1030 #endif
1031
1032 static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
1033 {
1034 /* Special null first entry.
1035 A `num' value of zero is thus invalid.
1036 Also, the special `invalid' insn resides here. */
1037 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
1038 /* add $reg8,$pof$upof16 */
1039 {
1040 XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
1041 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1042 },
1043 /* sub $reg8,$pof$upof16 */
1044 {
1045 XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
1046 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1047 },
1048 /* addb $regb8,$pof$upof16 */
1049 {
1050 XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
1051 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1052 },
1053 /* subb $regb8,$pof$upof16 */
1054 {
1055 XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
1056 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1057 },
1058 /* add $reg8,$pag$upag16 */
1059 {
1060 XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
1061 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1062 },
1063 /* sub $reg8,$pag$upag16 */
1064 {
1065 XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
1066 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1067 },
1068 /* addb $regb8,$pag$upag16 */
1069 {
1070 XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
1071 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1072 },
1073 /* subb $regb8,$pag$upag16 */
1074 {
1075 XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
1076 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1077 },
1078 /* addc $reg8,$pof$upof16 */
1079 {
1080 XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
1081 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1082 },
1083 /* subc $reg8,$pof$upof16 */
1084 {
1085 XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
1086 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1087 },
1088 /* addcb $regb8,$pof$upof16 */
1089 {
1090 XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
1091 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1092 },
1093 /* subcb $regb8,$pof$upof16 */
1094 {
1095 XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
1096 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1097 },
1098 /* addc $reg8,$pag$upag16 */
1099 {
1100 XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
1101 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1102 },
1103 /* subc $reg8,$pag$upag16 */
1104 {
1105 XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
1106 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1107 },
1108 /* addcb $regb8,$pag$upag16 */
1109 {
1110 XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
1111 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1112 },
1113 /* subcb $regb8,$pag$upag16 */
1114 {
1115 XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
1116 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1117 },
1118 /* add $pof$upof16,$reg8 */
1119 {
1120 XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
1121 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1122 },
1123 /* sub $pof$upof16,$reg8 */
1124 {
1125 XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
1126 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1127 },
1128 /* addb $pof$upof16,$regb8 */
1129 {
1130 XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
1131 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1132 },
1133 /* subb $pof$upof16,$regb8 */
1134 {
1135 XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
1136 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1137 },
1138 /* addc $pof$upof16,$reg8 */
1139 {
1140 XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
1141 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1142 },
1143 /* subc $pof$upof16,$reg8 */
1144 {
1145 XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
1146 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1147 },
1148 /* addcb $pof$upof16,$regb8 */
1149 {
1150 XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
1151 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1152 },
1153 /* subcb $pof$upof16,$regb8 */
1154 {
1155 XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
1156 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1157 },
1158 /* add $reg8,$hash$pof$uimm16 */
1159 {
1160 XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
1161 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1162 },
1163 /* sub $reg8,$hash$pof$uimm16 */
1164 {
1165 XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
1166 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1167 },
1168 /* add $reg8,$hash$pag$uimm16 */
1169 {
1170 XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
1171 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1172 },
1173 /* sub $reg8,$hash$pag$uimm16 */
1174 {
1175 XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
1176 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1177 },
1178 /* add $dr,$hash$pof$uimm3 */
1179 {
1180 XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
1181 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1182 },
1183 /* sub $dr,$hash$pof$uimm3 */
1184 {
1185 XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
1186 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1187 },
1188 /* addb $drb,$hash$pag$uimm3 */
1189 {
1190 XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
1191 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1192 },
1193 /* subb $drb,$hash$pag$uimm3 */
1194 {
1195 XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
1196 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1197 },
1198 /* add $dr,$hash$pag$uimm3 */
1199 {
1200 XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
1201 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1202 },
1203 /* sub $dr,$hash$pag$uimm3 */
1204 {
1205 XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
1206 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1207 },
1208 /* addb $drb,$hash$pof$uimm3 */
1209 {
1210 XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
1211 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1212 },
1213 /* subb $drb,$hash$pof$uimm3 */
1214 {
1215 XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
1216 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1217 },
1218 /* addb $regb8,$hash$pof$uimm8 */
1219 {
1220 XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
1221 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1222 },
1223 /* subb $regb8,$hash$pof$uimm8 */
1224 {
1225 XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
1226 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1227 },
1228 /* addb $regb8,$hash$pag$uimm8 */
1229 {
1230 XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
1231 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1232 },
1233 /* subb $regb8,$hash$pag$uimm8 */
1234 {
1235 XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
1236 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1237 },
1238 /* addc $reg8,$hash$pof$uimm16 */
1239 {
1240 XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
1241 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1242 },
1243 /* subc $reg8,$hash$pof$uimm16 */
1244 {
1245 XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
1246 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1247 },
1248 /* addc $reg8,$hash$pag$uimm16 */
1249 {
1250 XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
1251 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1252 },
1253 /* subc $reg8,$hash$pag$uimm16 */
1254 {
1255 XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
1256 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1257 },
1258 /* addc $dr,$hash$pof$uimm3 */
1259 {
1260 XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
1261 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1262 },
1263 /* subc $dr,$hash$pof$uimm3 */
1264 {
1265 XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
1266 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1267 },
1268 /* addcb $drb,$hash$pag$uimm3 */
1269 {
1270 XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
1271 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1272 },
1273 /* subcb $drb,$hash$pag$uimm3 */
1274 {
1275 XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
1276 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1277 },
1278 /* addc $dr,$hash$pag$uimm3 */
1279 {
1280 XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
1281 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1282 },
1283 /* subc $dr,$hash$pag$uimm3 */
1284 {
1285 XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
1286 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1287 },
1288 /* addcb $drb,$hash$pof$uimm3 */
1289 {
1290 XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
1291 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1292 },
1293 /* subcb $drb,$hash$pof$uimm3 */
1294 {
1295 XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
1296 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1297 },
1298 /* addcb $regb8,$hash$pof$uimm8 */
1299 {
1300 XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
1301 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1302 },
1303 /* subcb $regb8,$hash$pof$uimm8 */
1304 {
1305 XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
1306 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1307 },
1308 /* addcb $regb8,$hash$pag$uimm8 */
1309 {
1310 XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
1311 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1312 },
1313 /* subcb $regb8,$hash$pag$uimm8 */
1314 {
1315 XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
1316 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1317 },
1318 /* add $dr,$hash$uimm3 */
1319 {
1320 XC16X_INSN_ADDRI, "addri", "add", 16,
1321 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1322 },
1323 /* sub $dr,$hash$uimm3 */
1324 {
1325 XC16X_INSN_SUBRI, "subri", "sub", 16,
1326 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1327 },
1328 /* addb $drb,$hash$uimm3 */
1329 {
1330 XC16X_INSN_ADDBRI, "addbri", "addb", 16,
1331 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1332 },
1333 /* subb $drb,$hash$uimm3 */
1334 {
1335 XC16X_INSN_SUBBRI, "subbri", "subb", 16,
1336 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1337 },
1338 /* add $reg8,$hash$uimm16 */
1339 {
1340 XC16X_INSN_ADDRIM, "addrim", "add", 32,
1341 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1342 },
1343 /* sub $reg8,$hash$uimm16 */
1344 {
1345 XC16X_INSN_SUBRIM, "subrim", "sub", 32,
1346 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1347 },
1348 /* addb $regb8,$hash$uimm8 */
1349 {
1350 XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
1351 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1352 },
1353 /* subb $regb8,$hash$uimm8 */
1354 {
1355 XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
1356 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1357 },
1358 /* addc $dr,$hash$uimm3 */
1359 {
1360 XC16X_INSN_ADDCRI, "addcri", "addc", 16,
1361 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1362 },
1363 /* subc $dr,$hash$uimm3 */
1364 {
1365 XC16X_INSN_SUBCRI, "subcri", "subc", 16,
1366 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1367 },
1368 /* addcb $drb,$hash$uimm3 */
1369 {
1370 XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
1371 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1372 },
1373 /* subcb $drb,$hash$uimm3 */
1374 {
1375 XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
1376 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1377 },
1378 /* addc $reg8,$hash$uimm16 */
1379 {
1380 XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
1381 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1382 },
1383 /* subc $reg8,$hash$uimm16 */
1384 {
1385 XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
1386 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1387 },
1388 /* addcb $regb8,$hash$uimm8 */
1389 {
1390 XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
1391 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1392 },
1393 /* subcb $regb8,$hash$uimm8 */
1394 {
1395 XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
1396 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1397 },
1398 /* add $dr,$sr */
1399 {
1400 XC16X_INSN_ADDR, "addr", "add", 16,
1401 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1402 },
1403 /* sub $dr,$sr */
1404 {
1405 XC16X_INSN_SUBR, "subr", "sub", 16,
1406 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1407 },
1408 /* addb $drb,$srb */
1409 {
1410 XC16X_INSN_ADDBR, "addbr", "addb", 16,
1411 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1412 },
1413 /* subb $drb,$srb */
1414 {
1415 XC16X_INSN_SUBBR, "subbr", "subb", 16,
1416 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1417 },
1418 /* add $dr,[$sr2] */
1419 {
1420 XC16X_INSN_ADD2, "add2", "add", 16,
1421 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1422 },
1423 /* sub $dr,[$sr2] */
1424 {
1425 XC16X_INSN_SUB2, "sub2", "sub", 16,
1426 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1427 },
1428 /* addb $drb,[$sr2] */
1429 {
1430 XC16X_INSN_ADDB2, "addb2", "addb", 16,
1431 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1432 },
1433 /* subb $drb,[$sr2] */
1434 {
1435 XC16X_INSN_SUBB2, "subb2", "subb", 16,
1436 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1437 },
1438 /* add $dr,[$sr2+] */
1439 {
1440 XC16X_INSN_ADD2I, "add2i", "add", 16,
1441 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1442 },
1443 /* sub $dr,[$sr2+] */
1444 {
1445 XC16X_INSN_SUB2I, "sub2i", "sub", 16,
1446 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1447 },
1448 /* addb $drb,[$sr2+] */
1449 {
1450 XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
1451 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1452 },
1453 /* subb $drb,[$sr2+] */
1454 {
1455 XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
1456 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1457 },
1458 /* addc $dr,$sr */
1459 {
1460 XC16X_INSN_ADDCR, "addcr", "addc", 16,
1461 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1462 },
1463 /* subc $dr,$sr */
1464 {
1465 XC16X_INSN_SUBCR, "subcr", "subc", 16,
1466 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1467 },
1468 /* addcb $drb,$srb */
1469 {
1470 XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
1471 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1472 },
1473 /* subcb $drb,$srb */
1474 {
1475 XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
1476 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1477 },
1478 /* addc $dr,[$sr2] */
1479 {
1480 XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
1481 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1482 },
1483 /* subc $dr,[$sr2] */
1484 {
1485 XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
1486 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1487 },
1488 /* addcb $drb,[$sr2] */
1489 {
1490 XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
1491 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1492 },
1493 /* subcb $drb,[$sr2] */
1494 {
1495 XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
1496 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1497 },
1498 /* addc $dr,[$sr2+] */
1499 {
1500 XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
1501 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1502 },
1503 /* subc $dr,[$sr2+] */
1504 {
1505 XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
1506 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1507 },
1508 /* addcb $drb,[$sr2+] */
1509 {
1510 XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
1511 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1512 },
1513 /* subcb $drb,[$sr2+] */
1514 {
1515 XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
1516 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1517 },
1518 /* add $regmem8,$memgr8 */
1519 {
1520 XC16X_INSN_ADDRM2, "addrm2", "add", 32,
1521 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1522 },
1523 /* add $memgr8,$regmem8 */
1524 {
1525 XC16X_INSN_ADDRM3, "addrm3", "add", 32,
1526 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1527 },
1528 /* add $reg8,$memory */
1529 {
1530 XC16X_INSN_ADDRM, "addrm", "add", 32,
1531 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1532 },
1533 /* add $memory,$reg8 */
1534 {
1535 XC16X_INSN_ADDRM1, "addrm1", "add", 32,
1536 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1537 },
1538 /* sub $regmem8,$memgr8 */
1539 {
1540 XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
1541 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1542 },
1543 /* sub $memgr8,$regmem8 */
1544 {
1545 XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
1546 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1547 },
1548 /* sub $reg8,$memory */
1549 {
1550 XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
1551 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1552 },
1553 /* sub $memory,$reg8 */
1554 {
1555 XC16X_INSN_SUBRM, "subrm", "sub", 32,
1556 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1557 },
1558 /* addb $regbmem8,$memgr8 */
1559 {
1560 XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
1561 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1562 },
1563 /* addb $memgr8,$regbmem8 */
1564 {
1565 XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
1566 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1567 },
1568 /* addb $regb8,$memory */
1569 {
1570 XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
1571 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1572 },
1573 /* addb $memory,$regb8 */
1574 {
1575 XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
1576 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1577 },
1578 /* subb $regbmem8,$memgr8 */
1579 {
1580 XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
1581 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1582 },
1583 /* subb $memgr8,$regbmem8 */
1584 {
1585 XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
1586 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1587 },
1588 /* subb $regb8,$memory */
1589 {
1590 XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
1591 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1592 },
1593 /* subb $memory,$regb8 */
1594 {
1595 XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
1596 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1597 },
1598 /* addc $regmem8,$memgr8 */
1599 {
1600 XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
1601 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1602 },
1603 /* addc $memgr8,$regmem8 */
1604 {
1605 XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
1606 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1607 },
1608 /* addc $reg8,$memory */
1609 {
1610 XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
1611 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1612 },
1613 /* addc $memory,$reg8 */
1614 {
1615 XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
1616 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1617 },
1618 /* subc $regmem8,$memgr8 */
1619 {
1620 XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
1621 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1622 },
1623 /* subc $memgr8,$regmem8 */
1624 {
1625 XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
1626 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1627 },
1628 /* subc $reg8,$memory */
1629 {
1630 XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
1631 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1632 },
1633 /* subc $memory,$reg8 */
1634 {
1635 XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
1636 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1637 },
1638 /* addcb $regbmem8,$memgr8 */
1639 {
1640 XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
1641 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1642 },
1643 /* addcb $memgr8,$regbmem8 */
1644 {
1645 XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
1646 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1647 },
1648 /* addcb $regb8,$memory */
1649 {
1650 XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
1651 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1652 },
1653 /* addcb $memory,$regb8 */
1654 {
1655 XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
1656 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1657 },
1658 /* subcb $regbmem8,$memgr8 */
1659 {
1660 XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
1661 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1662 },
1663 /* subcb $memgr8,$regbmem8 */
1664 {
1665 XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
1666 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1667 },
1668 /* subcb $regb8,$memory */
1669 {
1670 XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
1671 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1672 },
1673 /* subcb $memory,$regb8 */
1674 {
1675 XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
1676 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1677 },
1678 /* mul $src1,$src2 */
1679 {
1680 XC16X_INSN_MULS, "muls", "mul", 16,
1681 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1682 },
1683 /* mulu $src1,$src2 */
1684 {
1685 XC16X_INSN_MULU, "mulu", "mulu", 16,
1686 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1687 },
1688 /* div $srdiv */
1689 {
1690 XC16X_INSN_DIV, "div", "div", 16,
1691 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1692 },
1693 /* divl $srdiv */
1694 {
1695 XC16X_INSN_DIVL, "divl", "divl", 16,
1696 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1697 },
1698 /* divlu $srdiv */
1699 {
1700 XC16X_INSN_DIVLU, "divlu", "divlu", 16,
1701 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1702 },
1703 /* divu $srdiv */
1704 {
1705 XC16X_INSN_DIVU, "divu", "divu", 16,
1706 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1707 },
1708 /* cpl $dr */
1709 {
1710 XC16X_INSN_CPL, "cpl", "cpl", 16,
1711 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1712 },
1713 /* cplb $drb */
1714 {
1715 XC16X_INSN_CPLB, "cplb", "cplb", 16,
1716 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1717 },
1718 /* neg $dr */
1719 {
1720 XC16X_INSN_NEG, "neg", "neg", 16,
1721 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1722 },
1723 /* negb $drb */
1724 {
1725 XC16X_INSN_NEGB, "negb", "negb", 16,
1726 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1727 },
1728 /* and $dr,$sr */
1729 {
1730 XC16X_INSN_ANDR, "andr", "and", 16,
1731 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1732 },
1733 /* or $dr,$sr */
1734 {
1735 XC16X_INSN_ORR, "orr", "or", 16,
1736 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1737 },
1738 /* xor $dr,$sr */
1739 {
1740 XC16X_INSN_XORR, "xorr", "xor", 16,
1741 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1742 },
1743 /* andb $drb,$srb */
1744 {
1745 XC16X_INSN_ANDBR, "andbr", "andb", 16,
1746 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1747 },
1748 /* orb $drb,$srb */
1749 {
1750 XC16X_INSN_ORBR, "orbr", "orb", 16,
1751 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1752 },
1753 /* xorb $drb,$srb */
1754 {
1755 XC16X_INSN_XORBR, "xorbr", "xorb", 16,
1756 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1757 },
1758 /* and $dr,$hash$uimm3 */
1759 {
1760 XC16X_INSN_ANDRI, "andri", "and", 16,
1761 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1762 },
1763 /* or $dr,$hash$uimm3 */
1764 {
1765 XC16X_INSN_ORRI, "orri", "or", 16,
1766 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1767 },
1768 /* xor $dr,$hash$uimm3 */
1769 {
1770 XC16X_INSN_XORRI, "xorri", "xor", 16,
1771 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1772 },
1773 /* andb $drb,$hash$uimm3 */
1774 {
1775 XC16X_INSN_ANDBRI, "andbri", "andb", 16,
1776 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1777 },
1778 /* orb $drb,$hash$uimm3 */
1779 {
1780 XC16X_INSN_ORBRI, "orbri", "orb", 16,
1781 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1782 },
1783 /* xorb $drb,$hash$uimm3 */
1784 {
1785 XC16X_INSN_XORBRI, "xorbri", "xorb", 16,
1786 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1787 },
1788 /* and $reg8,$hash$uimm16 */
1789 {
1790 XC16X_INSN_ANDRIM, "andrim", "and", 32,
1791 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1792 },
1793 /* or $reg8,$hash$uimm16 */
1794 {
1795 XC16X_INSN_ORRIM, "orrim", "or", 32,
1796 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1797 },
1798 /* xor $reg8,$hash$uimm16 */
1799 {
1800 XC16X_INSN_XORRIM, "xorrim", "xor", 32,
1801 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1802 },
1803 /* andb $regb8,$hash$uimm8 */
1804 {
1805 XC16X_INSN_ANDBRIM, "andbrim", "andb", 32,
1806 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1807 },
1808 /* orb $regb8,$hash$uimm8 */
1809 {
1810 XC16X_INSN_ORBRIM, "orbrim", "orb", 32,
1811 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1812 },
1813 /* xorb $regb8,$hash$uimm8 */
1814 {
1815 XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32,
1816 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1817 },
1818 /* and $dr,[$sr2] */
1819 {
1820 XC16X_INSN_AND2, "and2", "and", 16,
1821 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1822 },
1823 /* or $dr,[$sr2] */
1824 {
1825 XC16X_INSN_OR2, "or2", "or", 16,
1826 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1827 },
1828 /* xor $dr,[$sr2] */
1829 {
1830 XC16X_INSN_XOR2, "xor2", "xor", 16,
1831 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1832 },
1833 /* andb $drb,[$sr2] */
1834 {
1835 XC16X_INSN_ANDB2, "andb2", "andb", 16,
1836 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1837 },
1838 /* orb $drb,[$sr2] */
1839 {
1840 XC16X_INSN_ORB2, "orb2", "orb", 16,
1841 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1842 },
1843 /* xorb $drb,[$sr2] */
1844 {
1845 XC16X_INSN_XORB2, "xorb2", "xorb", 16,
1846 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1847 },
1848 /* and $dr,[$sr2+] */
1849 {
1850 XC16X_INSN_AND2I, "and2i", "and", 16,
1851 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1852 },
1853 /* or $dr,[$sr2+] */
1854 {
1855 XC16X_INSN_OR2I, "or2i", "or", 16,
1856 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1857 },
1858 /* xor $dr,[$sr2+] */
1859 {
1860 XC16X_INSN_XOR2I, "xor2i", "xor", 16,
1861 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1862 },
1863 /* andb $drb,[$sr2+] */
1864 {
1865 XC16X_INSN_ANDB2I, "andb2i", "andb", 16,
1866 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1867 },
1868 /* orb $drb,[$sr2+] */
1869 {
1870 XC16X_INSN_ORB2I, "orb2i", "orb", 16,
1871 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1872 },
1873 /* xorb $drb,[$sr2+] */
1874 {
1875 XC16X_INSN_XORB2I, "xorb2i", "xorb", 16,
1876 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1877 },
1878 /* and $pof$reg8,$upof16 */
1879 {
1880 XC16X_INSN_ANDPOFR, "andpofr", "and", 32,
1881 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1882 },
1883 /* or $pof$reg8,$upof16 */
1884 {
1885 XC16X_INSN_ORPOFR, "orpofr", "or", 32,
1886 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1887 },
1888 /* xor $pof$reg8,$upof16 */
1889 {
1890 XC16X_INSN_XORPOFR, "xorpofr", "xor", 32,
1891 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1892 },
1893 /* andb $pof$regb8,$upof16 */
1894 {
1895 XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32,
1896 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1897 },
1898 /* orb $pof$regb8,$upof16 */
1899 {
1900 XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32,
1901 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1902 },
1903 /* xorb $pof$regb8,$upof16 */
1904 {
1905 XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32,
1906 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1907 },
1908 /* and $pof$upof16,$reg8 */
1909 {
1910 XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32,
1911 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1912 },
1913 /* or $pof$upof16,$reg8 */
1914 {
1915 XC16X_INSN_ORRPOFR, "orrpofr", "or", 32,
1916 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1917 },
1918 /* xor $pof$upof16,$reg8 */
1919 {
1920 XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32,
1921 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1922 },
1923 /* andb $pof$upof16,$regb8 */
1924 {
1925 XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32,
1926 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1927 },
1928 /* orb $pof$upof16,$regb8 */
1929 {
1930 XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32,
1931 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1932 },
1933 /* xorb $pof$upof16,$regb8 */
1934 {
1935 XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32,
1936 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1937 },
1938 /* and $regmem8,$memgr8 */
1939 {
1940 XC16X_INSN_ANDRM2, "andrm2", "and", 32,
1941 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1942 },
1943 /* and $memgr8,$regmem8 */
1944 {
1945 XC16X_INSN_ANDRM3, "andrm3", "and", 32,
1946 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1947 },
1948 /* and $reg8,$memory */
1949 {
1950 XC16X_INSN_ANDRM, "andrm", "and", 32,
1951 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1952 },
1953 /* and $memory,$reg8 */
1954 {
1955 XC16X_INSN_ANDRM1, "andrm1", "and", 32,
1956 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1957 },
1958 /* or $regmem8,$memgr8 */
1959 {
1960 XC16X_INSN_ORRM3, "orrm3", "or", 32,
1961 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1962 },
1963 /* or $memgr8,$regmem8 */
1964 {
1965 XC16X_INSN_ORRM2, "orrm2", "or", 32,
1966 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1967 },
1968 /* or $reg8,$memory */
1969 {
1970 XC16X_INSN_ORRM1, "orrm1", "or", 32,
1971 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1972 },
1973 /* or $memory,$reg8 */
1974 {
1975 XC16X_INSN_ORRM, "orrm", "or", 32,
1976 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1977 },
1978 /* xor $regmem8,$memgr8 */
1979 {
1980 XC16X_INSN_XORRM3, "xorrm3", "xor", 32,
1981 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1982 },
1983 /* xor $memgr8,$regmem8 */
1984 {
1985 XC16X_INSN_XORRM2, "xorrm2", "xor", 32,
1986 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1987 },
1988 /* xor $reg8,$memory */
1989 {
1990 XC16X_INSN_XORRM1, "xorrm1", "xor", 32,
1991 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1992 },
1993 /* xor $memory,$reg8 */
1994 {
1995 XC16X_INSN_XORRM, "xorrm", "xor", 32,
1996 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1997 },
1998 /* andb $regbmem8,$memgr8 */
1999 {
2000 XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32,
2001 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2002 },
2003 /* andb $memgr8,$regbmem8 */
2004 {
2005 XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32,
2006 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2007 },
2008 /* andb $regb8,$memory */
2009 {
2010 XC16X_INSN_ANDBRM, "andbrm", "andb", 32,
2011 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2012 },
2013 /* andb $memory,$regb8 */
2014 {
2015 XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32,
2016 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2017 },
2018 /* orb $regbmem8,$memgr8 */
2019 {
2020 XC16X_INSN_ORBRM3, "orbrm3", "orb", 32,
2021 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2022 },
2023 /* orb $memgr8,$regbmem8 */
2024 {
2025 XC16X_INSN_ORBRM2, "orbrm2", "orb", 32,
2026 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2027 },
2028 /* orb $regb8,$memory */
2029 {
2030 XC16X_INSN_ORBRM1, "orbrm1", "orb", 32,
2031 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2032 },
2033 /* orb $memory,$regb8 */
2034 {
2035 XC16X_INSN_ORBRM, "orbrm", "orb", 32,
2036 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2037 },
2038 /* xorb $regbmem8,$memgr8 */
2039 {
2040 XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32,
2041 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2042 },
2043 /* xorb $memgr8,$regbmem8 */
2044 {
2045 XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32,
2046 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2047 },
2048 /* xorb $regb8,$memory */
2049 {
2050 XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32,
2051 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2052 },
2053 /* xorb $memory,$regb8 */
2054 {
2055 XC16X_INSN_XORBRM, "xorbrm", "xorb", 32,
2056 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2057 },
2058 /* mov $dr,$sr */
2059 {
2060 XC16X_INSN_MOVR, "movr", "mov", 16,
2061 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2062 },
2063 /* movb $drb,$srb */
2064 {
2065 XC16X_INSN_MOVRB, "movrb", "movb", 16,
2066 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2067 },
2068 /* mov $dri,$hash$u4 */
2069 {
2070 XC16X_INSN_MOVRI, "movri", "mov", 16,
2071 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2072 },
2073 /* movb $srb,$hash$u4 */
2074 {
2075 XC16X_INSN_MOVBRI, "movbri", "movb", 16,
2076 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2077 },
2078 /* mov $reg8,$hash$uimm16 */
2079 {
2080 XC16X_INSN_MOVI, "movi", "mov", 32,
2081 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2082 },
2083 /* movb $regb8,$hash$uimm8 */
2084 {
2085 XC16X_INSN_MOVBI, "movbi", "movb", 32,
2086 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2087 },
2088 /* mov $dr,[$sr] */
2089 {
2090 XC16X_INSN_MOVR2, "movr2", "mov", 16,
2091 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2092 },
2093 /* movb $drb,[$sr] */
2094 {
2095 XC16X_INSN_MOVBR2, "movbr2", "movb", 16,
2096 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2097 },
2098 /* mov [$sr],$dr */
2099 {
2100 XC16X_INSN_MOVRI2, "movri2", "mov", 16,
2101 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2102 },
2103 /* movb [$sr],$drb */
2104 {
2105 XC16X_INSN_MOVBRI2, "movbri2", "movb", 16,
2106 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2107 },
2108 /* mov [-$sr],$dr */
2109 {
2110 XC16X_INSN_MOVRI3, "movri3", "mov", 16,
2111 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2112 },
2113 /* movb [-$sr],$drb */
2114 {
2115 XC16X_INSN_MOVBRI3, "movbri3", "movb", 16,
2116 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2117 },
2118 /* mov $dr,[$sr+] */
2119 {
2120 XC16X_INSN_MOV2I, "mov2i", "mov", 16,
2121 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2122 },
2123 /* movb $drb,[$sr+] */
2124 {
2125 XC16X_INSN_MOVB2I, "movb2i", "movb", 16,
2126 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2127 },
2128 /* mov [$dr],[$sr] */
2129 {
2130 XC16X_INSN_MOV6I, "mov6i", "mov", 16,
2131 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2132 },
2133 /* movb [$dr],[$sr] */
2134 {
2135 XC16X_INSN_MOVB6I, "movb6i", "movb", 16,
2136 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2137 },
2138 /* mov [$dr+],[$sr] */
2139 {
2140 XC16X_INSN_MOV7I, "mov7i", "mov", 16,
2141 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2142 },
2143 /* movb [$dr+],[$sr] */
2144 {
2145 XC16X_INSN_MOVB7I, "movb7i", "movb", 16,
2146 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2147 },
2148 /* mov [$dr],[$sr+] */
2149 {
2150 XC16X_INSN_MOV8I, "mov8i", "mov", 16,
2151 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2152 },
2153 /* movb [$dr],[$sr+] */
2154 {
2155 XC16X_INSN_MOVB8I, "movb8i", "movb", 16,
2156 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2157 },
2158 /* mov $dr,[$sr+$hash$uimm16] */
2159 {
2160 XC16X_INSN_MOV9I, "mov9i", "mov", 32,
2161 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2162 },
2163 /* movb $drb,[$sr+$hash$uimm16] */
2164 {
2165 XC16X_INSN_MOVB9I, "movb9i", "movb", 32,
2166 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2167 },
2168 /* mov [$sr+$hash$uimm16],$dr */
2169 {
2170 XC16X_INSN_MOV10I, "mov10i", "mov", 32,
2171 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2172 },
2173 /* movb [$sr+$hash$uimm16],$drb */
2174 {
2175 XC16X_INSN_MOVB10I, "movb10i", "movb", 32,
2176 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2177 },
2178 /* mov [$src2],$memory */
2179 {
2180 XC16X_INSN_MOVRI11, "movri11", "mov", 32,
2181 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2182 },
2183 /* movb [$src2],$memory */
2184 {
2185 XC16X_INSN_MOVBRI11, "movbri11", "movb", 32,
2186 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2187 },
2188 /* mov $memory,[$src2] */
2189 {
2190 XC16X_INSN_MOVRI12, "movri12", "mov", 32,
2191 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2192 },
2193 /* movb $memory,[$src2] */
2194 {
2195 XC16X_INSN_MOVBRI12, "movbri12", "movb", 32,
2196 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2197 },
2198 /* mov $regoff8,$hash$pof$upof16 */
2199 {
2200 XC16X_INSN_MOVEHM5, "movehm5", "mov", 32,
2201 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2202 },
2203 /* mov $regoff8,$hash$pag$upag16 */
2204 {
2205 XC16X_INSN_MOVEHM6, "movehm6", "mov", 32,
2206 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2207 },
2208 /* mov $regoff8,$hash$segm$useg16 */
2209 {
2210 XC16X_INSN_MOVEHM7, "movehm7", "mov", 32,
2211 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2212 },
2213 /* mov $regoff8,$hash$sof$usof16 */
2214 {
2215 XC16X_INSN_MOVEHM8, "movehm8", "mov", 32,
2216 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2217 },
2218 /* movb $regb8,$hash$pof$uimm8 */
2219 {
2220 XC16X_INSN_MOVEHM9, "movehm9", "movb", 32,
2221 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2222 },
2223 /* movb $regoff8,$hash$pag$uimm8 */
2224 {
2225 XC16X_INSN_MOVEHM10, "movehm10", "movb", 32,
2226 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2227 },
2228 /* mov $regoff8,$pof$upof16 */
2229 {
2230 XC16X_INSN_MOVRMP, "movrmp", "mov", 32,
2231 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2232 },
2233 /* movb $regb8,$pof$upof16 */
2234 {
2235 XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32,
2236 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2237 },
2238 /* mov $regoff8,$pag$upag16 */
2239 {
2240 XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32,
2241 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2242 },
2243 /* movb $regb8,$pag$upag16 */
2244 {
2245 XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32,
2246 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2247 },
2248 /* mov $pof$upof16,$regoff8 */
2249 {
2250 XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32,
2251 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2252 },
2253 /* movb $pof$upof16,$regb8 */
2254 {
2255 XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32,
2256 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2257 },
2258 /* mov $dri,$hash$pof$u4 */
2259 {
2260 XC16X_INSN_MOVEHM1, "movehm1", "mov", 16,
2261 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2262 },
2263 /* movb $srb,$hash$pof$u4 */
2264 {
2265 XC16X_INSN_MOVEHM2, "movehm2", "movb", 16,
2266 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2267 },
2268 /* mov $dri,$hash$pag$u4 */
2269 {
2270 XC16X_INSN_MOVEHM3, "movehm3", "mov", 16,
2271 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2272 },
2273 /* movb $srb,$hash$pag$u4 */
2274 {
2275 XC16X_INSN_MOVEHM4, "movehm4", "movb", 16,
2276 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2277 },
2278 /* mov $regmem8,$memgr8 */
2279 {
2280 XC16X_INSN_MVE12, "mve12", "mov", 32,
2281 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2282 },
2283 /* mov $memgr8,$regmem8 */
2284 {
2285 XC16X_INSN_MVE13, "mve13", "mov", 32,
2286 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2287 },
2288 /* mov $reg8,$memory */
2289 {
2290 XC16X_INSN_MOVER12, "mover12", "mov", 32,
2291 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2292 },
2293 /* mov $memory,$reg8 */
2294 {
2295 XC16X_INSN_MVR13, "mvr13", "mov", 32,
2296 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2297 },
2298 /* movb $regbmem8,$memgr8 */
2299 {
2300 XC16X_INSN_MVER12, "mver12", "movb", 32,
2301 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2302 },
2303 /* movb $memgr8,$regbmem8 */
2304 {
2305 XC16X_INSN_MVER13, "mver13", "movb", 32,
2306 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2307 },
2308 /* movb $regb8,$memory */
2309 {
2310 XC16X_INSN_MOVR12, "movr12", "movb", 32,
2311 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2312 },
2313 /* movb $memory,$regb8 */
2314 {
2315 XC16X_INSN_MOVR13, "movr13", "movb", 32,
2316 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2317 },
2318 /* movbs $sr,$drb */
2319 {
2320 XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16,
2321 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2322 },
2323 /* movbz $sr,$drb */
2324 {
2325 XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16,
2326 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2327 },
2328 /* movbs $regmem8,$pof$upof16 */
2329 {
2330 XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32,
2331 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2332 },
2333 /* movbs $pof$upof16,$regbmem8 */
2334 {
2335 XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32,
2336 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2337 },
2338 /* movbz $reg8,$pof$upof16 */
2339 {
2340 XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32,
2341 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2342 },
2343 /* movbz $pof$upof16,$regb8 */
2344 {
2345 XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32,
2346 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2347 },
2348 /* movbs $regmem8,$memgr8 */
2349 {
2350 XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32,
2351 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2352 },
2353 /* movbs $memgr8,$regbmem8 */
2354 {
2355 XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32,
2356 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2357 },
2358 /* movbs $reg8,$memory */
2359 {
2360 XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32,
2361 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2362 },
2363 /* movbs $memory,$regb8 */
2364 {
2365 XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32,
2366 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2367 },
2368 /* movbz $regmem8,$memgr8 */
2369 {
2370 XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32,
2371 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2372 },
2373 /* movbz $memgr8,$regbmem8 */
2374 {
2375 XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32,
2376 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2377 },
2378 /* movbz $reg8,$memory */
2379 {
2380 XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32,
2381 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2382 },
2383 /* movbz $memory,$regb8 */
2384 {
2385 XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32,
2386 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2387 },
2388 /* movbs $sr,$drb */
2389 {
2390 XC16X_INSN_MOVRBS, "movrbs", "movbs", 16,
2391 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2392 },
2393 /* movbz $sr,$drb */
2394 {
2395 XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16,
2396 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2397 },
2398 /* jmpa+ $extcond,$caddr */
2399 {
2400 XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32,
2401 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2402 },
2403 /* jmpa $extcond,$caddr */
2404 {
2405 XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32,
2406 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2407 },
2408 /* jmpa- $extcond,$caddr */
2409 {
2410 XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32,
2411 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2412 },
2413 /* jmpi $icond,[$sr] */
2414 {
2415 XC16X_INSN_JMPI, "jmpi", "jmpi", 16,
2416 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2417 },
2418 /* jmpr $cond,$rel */
2419 {
2420 XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16,
2421 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2422 },
2423 /* jmpr $cond,$rel */
2424 {
2425 XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16,
2426 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2427 },
2428 /* jmpr $cond,$rel */
2429 {
2430 XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16,
2431 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2432 },
2433 /* jmpr $cond,$rel */
2434 {
2435 XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16,
2436 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2437 },
2438 /* jmpr $cond,$rel */
2439 {
2440 XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16,
2441 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2442 },
2443 /* jmpr $cond,$rel */
2444 {
2445 XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16,
2446 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2447 },
2448 /* jmpr $cond,$rel */
2449 {
2450 XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16,
2451 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2452 },
2453 /* jmpr $cond,$rel */
2454 {
2455 XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16,
2456 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2457 },
2458 /* jmpr $cond,$rel */
2459 {
2460 XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16,
2461 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2462 },
2463 /* jmpr $cond,$rel */
2464 {
2465 XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16,
2466 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2467 },
2468 /* jmpr $cond,$rel */
2469 {
2470 XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16,
2471 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2472 },
2473 /* jmpr $cond,$rel */
2474 {
2475 XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16,
2476 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2477 },
2478 /* jmpr $cond,$rel */
2479 {
2480 XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16,
2481 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2482 },
2483 /* jmpr $cond,$rel */
2484 {
2485 XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16,
2486 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2487 },
2488 /* jmpr $cond,$rel */
2489 {
2490 XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16,
2491 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2492 },
2493 /* jmpr $cond,$rel */
2494 {
2495 XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16,
2496 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2497 },
2498 /* jmpr $cond,$rel */
2499 {
2500 XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16,
2501 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2502 },
2503 /* jmpr $cond,$rel */
2504 {
2505 XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16,
2506 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2507 },
2508 /* jmpr $cond,$rel */
2509 {
2510 XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16,
2511 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2512 },
2513 /* jmpr $cond,$rel */
2514 {
2515 XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16,
2516 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2517 },
2518 /* jmps $hash$segm$useg8,$hash$sof$usof16 */
2519 {
2520 XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32,
2521 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2522 },
2523 /* jmps $seg,$caddr */
2524 {
2525 XC16X_INSN_JMPS, "jmps", "jmps", 32,
2526 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2527 },
2528 /* jb $genreg$dot$qlobit,$relhi */
2529 {
2530 XC16X_INSN_JB, "jb", "jb", 32,
2531 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2532 },
2533 /* jbc $genreg$dot$qlobit,$relhi */
2534 {
2535 XC16X_INSN_JBC, "jbc", "jbc", 32,
2536 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2537 },
2538 /* jnb $genreg$dot$qlobit,$relhi */
2539 {
2540 XC16X_INSN_JNB, "jnb", "jnb", 32,
2541 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2542 },
2543 /* jnbs $genreg$dot$qlobit,$relhi */
2544 {
2545 XC16X_INSN_JNBS, "jnbs", "jnbs", 32,
2546 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2547 },
2548 /* calla+ $extcond,$caddr */
2549 {
2550 XC16X_INSN_CALLA0, "calla0", "calla+", 32,
2551 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2552 },
2553 /* calla $extcond,$caddr */
2554 {
2555 XC16X_INSN_CALLA1, "calla1", "calla", 32,
2556 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2557 },
2558 /* calla- $extcond,$caddr */
2559 {
2560 XC16X_INSN_CALLA_, "calla-", "calla-", 32,
2561 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2562 },
2563 /* calli $icond,[$sr] */
2564 {
2565 XC16X_INSN_CALLI, "calli", "calli", 16,
2566 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2567 },
2568 /* callr $rel */
2569 {
2570 XC16X_INSN_CALLR, "callr", "callr", 16,
2571 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2572 },
2573 /* calls $hash$segm$useg8,$hash$sof$usof16 */
2574 {
2575 XC16X_INSN_CALLSEG, "callseg", "calls", 32,
2576 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2577 },
2578 /* calls $seg,$caddr */
2579 {
2580 XC16X_INSN_CALLS, "calls", "calls", 32,
2581 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2582 },
2583 /* pcall $reg8,$caddr */
2584 {
2585 XC16X_INSN_PCALL, "pcall", "pcall", 32,
2586 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2587 },
2588 /* trap $hash$uimm7 */
2589 {
2590 XC16X_INSN_TRAP, "trap", "trap", 16,
2591 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2592 },
2593 /* ret */
2594 {
2595 XC16X_INSN_RET, "ret", "ret", 16,
2596 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2597 },
2598 /* rets */
2599 {
2600 XC16X_INSN_RETS, "rets", "rets", 16,
2601 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2602 },
2603 /* retp $reg8 */
2604 {
2605 XC16X_INSN_RETP, "retp", "retp", 16,
2606 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2607 },
2608 /* reti */
2609 {
2610 XC16X_INSN_RETI, "reti", "reti", 16,
2611 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2612 },
2613 /* pop $reg8 */
2614 {
2615 XC16X_INSN_POP, "pop", "pop", 16,
2616 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2617 },
2618 /* push $reg8 */
2619 {
2620 XC16X_INSN_PUSH, "push", "push", 16,
2621 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2622 },
2623 /* scxt $reg8,$hash$uimm16 */
2624 {
2625 XC16X_INSN_SCXTI, "scxti", "scxt", 32,
2626 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2627 },
2628 /* scxt $reg8,$pof$upof16 */
2629 {
2630 XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32,
2631 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2632 },
2633 /* scxt $regmem8,$memgr8 */
2634 {
2635 XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32,
2636 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2637 },
2638 /* scxt $reg8,$memory */
2639 {
2640 XC16X_INSN_SCXTM, "scxtm", "scxt", 32,
2641 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2642 },
2643 /* nop */
2644 {
2645 XC16X_INSN_NOP, "nop", "nop", 16,
2646 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2647 },
2648 /* srst */
2649 {
2650 XC16X_INSN_SRSTM, "srstm", "srst", 32,
2651 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2652 },
2653 /* idle */
2654 {
2655 XC16X_INSN_IDLEM, "idlem", "idle", 32,
2656 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2657 },
2658 /* pwrdn */
2659 {
2660 XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32,
2661 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2662 },
2663 /* diswdt */
2664 {
2665 XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32,
2666 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2667 },
2668 /* enwdt */
2669 {
2670 XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32,
2671 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2672 },
2673 /* einit */
2674 {
2675 XC16X_INSN_EINITM, "einitm", "einit", 32,
2676 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2677 },
2678 /* srvwdt */
2679 {
2680 XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32,
2681 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2682 },
2683 /* sbrk */
2684 {
2685 XC16X_INSN_SBRK, "sbrk", "sbrk", 16,
2686 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2687 },
2688 /* atomic $hash$uimm2 */
2689 {
2690 XC16X_INSN_ATOMIC, "atomic", "atomic", 16,
2691 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2692 },
2693 /* extr $hash$uimm2 */
2694 {
2695 XC16X_INSN_EXTR, "extr", "extr", 16,
2696 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2697 },
2698 /* extp $sr,$hash$uimm2 */
2699 {
2700 XC16X_INSN_EXTP, "extp", "extp", 16,
2701 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2702 },
2703 /* extp $hash$pagenum,$hash$uimm2 */
2704 {
2705 XC16X_INSN_EXTP1, "extp1", "extp", 32,
2706 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2707 },
2708 /* extp $hash$pag$upag16,$hash$uimm2 */
2709 {
2710 XC16X_INSN_EXTPG1, "extpg1", "extp", 32,
2711 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2712 },
2713 /* extpr $sr,$hash$uimm2 */
2714 {
2715 XC16X_INSN_EXTPR, "extpr", "extpr", 16,
2716 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2717 },
2718 /* extpr $hash$pagenum,$hash$uimm2 */
2719 {
2720 XC16X_INSN_EXTPR1, "extpr1", "extpr", 32,
2721 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2722 },
2723 /* exts $sr,$hash$uimm2 */
2724 {
2725 XC16X_INSN_EXTS, "exts", "exts", 16,
2726 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2727 },
2728 /* exts $hash$seghi8,$hash$uimm2 */
2729 {
2730 XC16X_INSN_EXTS1, "exts1", "exts", 32,
2731 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2732 },
2733 /* extsr $sr,$hash$uimm2 */
2734 {
2735 XC16X_INSN_EXTSR, "extsr", "extsr", 16,
2736 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2737 },
2738 /* extsr $hash$seghi8,$hash$uimm2 */
2739 {
2740 XC16X_INSN_EXTSR1, "extsr1", "extsr", 32,
2741 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2742 },
2743 /* prior $dr,$sr */
2744 {
2745 XC16X_INSN_PRIOR, "prior", "prior", 16,
2746 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2747 },
2748 /* bclr $RegNam */
2749 {
2750 XC16X_INSN_BCLR18, "bclr18", "bclr", 16,
2751 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2752 },
2753 /* bclr $reg8$dot$qbit */
2754 {
2755 XC16X_INSN_BCLR0, "bclr0", "bclr", 16,
2756 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2757 },
2758 /* bclr $reg8$dot$qbit */
2759 {
2760 XC16X_INSN_BCLR1, "bclr1", "bclr", 16,
2761 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2762 },
2763 /* bclr $reg8$dot$qbit */
2764 {
2765 XC16X_INSN_BCLR2, "bclr2", "bclr", 16,
2766 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2767 },
2768 /* bclr $reg8$dot$qbit */
2769 {
2770 XC16X_INSN_BCLR3, "bclr3", "bclr", 16,
2771 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2772 },
2773 /* bclr $reg8$dot$qbit */
2774 {
2775 XC16X_INSN_BCLR4, "bclr4", "bclr", 16,
2776 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2777 },
2778 /* bclr $reg8$dot$qbit */
2779 {
2780 XC16X_INSN_BCLR5, "bclr5", "bclr", 16,
2781 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2782 },
2783 /* bclr $reg8$dot$qbit */
2784 {
2785 XC16X_INSN_BCLR6, "bclr6", "bclr", 16,
2786 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2787 },
2788 /* bclr $reg8$dot$qbit */
2789 {
2790 XC16X_INSN_BCLR7, "bclr7", "bclr", 16,
2791 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2792 },
2793 /* bclr $reg8$dot$qbit */
2794 {
2795 XC16X_INSN_BCLR8, "bclr8", "bclr", 16,
2796 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2797 },
2798 /* bclr $reg8$dot$qbit */
2799 {
2800 XC16X_INSN_BCLR9, "bclr9", "bclr", 16,
2801 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2802 },
2803 /* bclr $reg8$dot$qbit */
2804 {
2805 XC16X_INSN_BCLR10, "bclr10", "bclr", 16,
2806 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2807 },
2808 /* bclr $reg8$dot$qbit */
2809 {
2810 XC16X_INSN_BCLR11, "bclr11", "bclr", 16,
2811 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2812 },
2813 /* bclr $reg8$dot$qbit */
2814 {
2815 XC16X_INSN_BCLR12, "bclr12", "bclr", 16,
2816 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2817 },
2818 /* bclr $reg8$dot$qbit */
2819 {
2820 XC16X_INSN_BCLR13, "bclr13", "bclr", 16,
2821 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2822 },
2823 /* bclr $reg8$dot$qbit */
2824 {
2825 XC16X_INSN_BCLR14, "bclr14", "bclr", 16,
2826 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2827 },
2828 /* bclr $reg8$dot$qbit */
2829 {
2830 XC16X_INSN_BCLR15, "bclr15", "bclr", 16,
2831 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2832 },
2833 /* bset $RegNam */
2834 {
2835 XC16X_INSN_BSET19, "bset19", "bset", 16,
2836 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2837 },
2838 /* bset $reg8$dot$qbit */
2839 {
2840 XC16X_INSN_BSET0, "bset0", "bset", 16,
2841 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2842 },
2843 /* bset $reg8$dot$qbit */
2844 {
2845 XC16X_INSN_BSET1, "bset1", "bset", 16,
2846 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2847 },
2848 /* bset $reg8$dot$qbit */
2849 {
2850 XC16X_INSN_BSET2, "bset2", "bset", 16,
2851 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2852 },
2853 /* bset $reg8$dot$qbit */
2854 {
2855 XC16X_INSN_BSET3, "bset3", "bset", 16,
2856 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2857 },
2858 /* bset $reg8$dot$qbit */
2859 {
2860 XC16X_INSN_BSET4, "bset4", "bset", 16,
2861 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2862 },
2863 /* bset $reg8$dot$qbit */
2864 {
2865 XC16X_INSN_BSET5, "bset5", "bset", 16,
2866 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2867 },
2868 /* bset $reg8$dot$qbit */
2869 {
2870 XC16X_INSN_BSET6, "bset6", "bset", 16,
2871 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2872 },
2873 /* bset $reg8$dot$qbit */
2874 {
2875 XC16X_INSN_BSET7, "bset7", "bset", 16,
2876 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2877 },
2878 /* bset $reg8$dot$qbit */
2879 {
2880 XC16X_INSN_BSET8, "bset8", "bset", 16,
2881 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2882 },
2883 /* bset $reg8$dot$qbit */
2884 {
2885 XC16X_INSN_BSET9, "bset9", "bset", 16,
2886 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2887 },
2888 /* bset $reg8$dot$qbit */
2889 {
2890 XC16X_INSN_BSET10, "bset10", "bset", 16,
2891 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2892 },
2893 /* bset $reg8$dot$qbit */
2894 {
2895 XC16X_INSN_BSET11, "bset11", "bset", 16,
2896 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2897 },
2898 /* bset $reg8$dot$qbit */
2899 {
2900 XC16X_INSN_BSET12, "bset12", "bset", 16,
2901 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2902 },
2903 /* bset $reg8$dot$qbit */
2904 {
2905 XC16X_INSN_BSET13, "bset13", "bset", 16,
2906 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2907 },
2908 /* bset $reg8$dot$qbit */
2909 {
2910 XC16X_INSN_BSET14, "bset14", "bset", 16,
2911 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2912 },
2913 /* bset $reg8$dot$qbit */
2914 {
2915 XC16X_INSN_BSET15, "bset15", "bset", 16,
2916 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2917 },
2918 /* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
2919 {
2920 XC16X_INSN_BMOV, "bmov", "bmov", 32,
2921 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2922 },
2923 /* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
2924 {
2925 XC16X_INSN_BMOVN, "bmovn", "bmovn", 32,
2926 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2927 },
2928 /* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
2929 {
2930 XC16X_INSN_BAND, "band", "band", 32,
2931 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2932 },
2933 /* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
2934 {
2935 XC16X_INSN_BOR, "bor", "bor", 32,
2936 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2937 },
2938 /* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
2939 {
2940 XC16X_INSN_BXOR, "bxor", "bxor", 32,
2941 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2942 },
2943 /* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
2944 {
2945 XC16X_INSN_BCMP, "bcmp", "bcmp", 32,
2946 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2947 },
2948 /* bfldl $reg8,$hash$mask8,$hash$datahi8 */
2949 {
2950 XC16X_INSN_BFLDL, "bfldl", "bfldl", 32,
2951 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2952 },
2953 /* bfldh $reg8,$hash$masklo8,$hash$data8 */
2954 {
2955 XC16X_INSN_BFLDH, "bfldh", "bfldh", 32,
2956 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2957 },
2958 /* cmp $src1,$src2 */
2959 {
2960 XC16X_INSN_CMPR, "cmpr", "cmp", 16,
2961 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2962 },
2963 /* cmpb $drb,$srb */
2964 {
2965 XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16,
2966 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2967 },
2968 /* cmp $src1,$hash$uimm3 */
2969 {
2970 XC16X_INSN_CMPRI, "cmpri", "cmp", 16,
2971 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2972 },
2973 /* cmpb $drb,$hash$uimm3 */
2974 {
2975 XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16,
2976 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2977 },
2978 /* cmp $reg8,$hash$uimm16 */
2979 {
2980 XC16X_INSN_CMPI, "cmpi", "cmp", 32,
2981 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2982 },
2983 /* cmpb $regb8,$hash$uimm8 */
2984 {
2985 XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32,
2986 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2987 },
2988 /* cmp $dr,[$sr2] */
2989 {
2990 XC16X_INSN_CMPR2, "cmpr2", "cmp", 16,
2991 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2992 },
2993 /* cmpb $drb,[$sr2] */
2994 {
2995 XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16,
2996 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2997 },
2998 /* cmp $dr,[$sr2+] */
2999 {
3000 XC16X_INSN_CMP2I, "cmp2i", "cmp", 16,
3001 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3002 },
3003 /* cmpb $drb,[$sr2+] */
3004 {
3005 XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16,
3006 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3007 },
3008 /* cmp $reg8,$pof$upof16 */
3009 {
3010 XC16X_INSN_CMP04, "cmp04", "cmp", 32,
3011 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3012 },
3013 /* cmpb $regb8,$pof$upof16 */
3014 {
3015 XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32,
3016 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3017 },
3018 /* cmp $regmem8,$memgr8 */
3019 {
3020 XC16X_INSN_CMP004, "cmp004", "cmp", 32,
3021 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3022 },
3023 /* cmp $reg8,$memory */
3024 {
3025 XC16X_INSN_CMP0004, "cmp0004", "cmp", 32,
3026 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3027 },
3028 /* cmpb $regbmem8,$memgr8 */
3029 {
3030 XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32,
3031 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3032 },
3033 /* cmpb $regb8,$memory */
3034 {
3035 XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32,
3036 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3037 },
3038 /* cmpd1 $sr,$hash$uimm4 */
3039 {
3040 XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16,
3041 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3042 },
3043 /* cmpd2 $sr,$hash$uimm4 */
3044 {
3045 XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16,
3046 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3047 },
3048 /* cmpi1 $sr,$hash$uimm4 */
3049 {
3050 XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16,
3051 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3052 },
3053 /* cmpi2 $sr,$hash$uimm4 */
3054 {
3055 XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16,
3056 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3057 },
3058 /* cmpd1 $reg8,$hash$uimm16 */
3059 {
3060 XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32,
3061 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3062 },
3063 /* cmpd2 $reg8,$hash$uimm16 */
3064 {
3065 XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32,
3066 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3067 },
3068 /* cmpi1 $reg8,$hash$uimm16 */
3069 {
3070 XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32,
3071 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3072 },
3073 /* cmpi2 $reg8,$hash$uimm16 */
3074 {
3075 XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32,
3076 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3077 },
3078 /* cmpd1 $reg8,$pof$upof16 */
3079 {
3080 XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32,
3081 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3082 },
3083 /* cmpd2 $reg8,$pof$upof16 */
3084 {
3085 XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32,
3086 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3087 },
3088 /* cmpi1 $reg8,$pof$upof16 */
3089 {
3090 XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32,
3091 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3092 },
3093 /* cmpi2 $reg8,$pof$upof16 */
3094 {
3095 XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32,
3096 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3097 },
3098 /* cmpd1 $regmem8,$memgr8 */
3099 {
3100 XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32,
3101 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3102 },
3103 /* cmpd2 $regmem8,$memgr8 */
3104 {
3105 XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32,
3106 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3107 },
3108 /* cmpi1 $regmem8,$memgr8 */
3109 {
3110 XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32,
3111 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3112 },
3113 /* cmpi2 $regmem8,$memgr8 */
3114 {
3115 XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32,
3116 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3117 },
3118 /* cmpd1 $reg8,$memory */
3119 {
3120 XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32,
3121 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3122 },
3123 /* cmpd2 $reg8,$memory */
3124 {
3125 XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32,
3126 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3127 },
3128 /* cmpi1 $reg8,$memory */
3129 {
3130 XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32,
3131 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3132 },
3133 /* cmpi2 $reg8,$memory */
3134 {
3135 XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32,
3136 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3137 },
3138 /* shl $dr,$sr */
3139 {
3140 XC16X_INSN_SHLR, "shlr", "shl", 16,
3141 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3142 },
3143 /* shr $dr,$sr */
3144 {
3145 XC16X_INSN_SHRR, "shrr", "shr", 16,
3146 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3147 },
3148 /* rol $dr,$sr */
3149 {
3150 XC16X_INSN_ROLR, "rolr", "rol", 16,
3151 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3152 },
3153 /* ror $dr,$sr */
3154 {
3155 XC16X_INSN_RORR, "rorr", "ror", 16,
3156 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3157 },
3158 /* ashr $dr,$sr */
3159 {
3160 XC16X_INSN_ASHRR, "ashrr", "ashr", 16,
3161 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3162 },
3163 /* shl $sr,$hash$uimm4 */
3164 {
3165 XC16X_INSN_SHLRI, "shlri", "shl", 16,
3166 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3167 },
3168 /* shr $sr,$hash$uimm4 */
3169 {
3170 XC16X_INSN_SHRRI, "shrri", "shr", 16,
3171 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3172 },
3173 /* rol $sr,$hash$uimm4 */
3174 {
3175 XC16X_INSN_ROLRI, "rolri", "rol", 16,
3176 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3177 },
3178 /* ror $sr,$hash$uimm4 */
3179 {
3180 XC16X_INSN_RORRI, "rorri", "ror", 16,
3181 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3182 },
3183 /* ashr $sr,$hash$uimm4 */
3184 {
3185 XC16X_INSN_ASHRRI, "ashrri", "ashr", 16,
3186 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3187 },
3188 };
3189
3190 #undef OP
3191 #undef A
3192
3193 /* Initialize anything needed to be done once, before any cpu_open call. */
3194
3195 static void
init_tables(void)3196 init_tables (void)
3197 {
3198 }
3199
3200 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
3201 static void build_hw_table (CGEN_CPU_TABLE *);
3202 static void build_ifield_table (CGEN_CPU_TABLE *);
3203 static void build_operand_table (CGEN_CPU_TABLE *);
3204 static void build_insn_table (CGEN_CPU_TABLE *);
3205 static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *);
3206
3207 /* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name. */
3208
3209 static const CGEN_MACH *
lookup_mach_via_bfd_name(const CGEN_MACH * table,const char * name)3210 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
3211 {
3212 while (table->name)
3213 {
3214 if (strcmp (name, table->bfd_name) == 0)
3215 return table;
3216 ++table;
3217 }
3218 abort ();
3219 }
3220
3221 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */
3222
3223 static void
build_hw_table(CGEN_CPU_TABLE * cd)3224 build_hw_table (CGEN_CPU_TABLE *cd)
3225 {
3226 int i;
3227 int machs = cd->machs;
3228 const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
3229 /* MAX_HW is only an upper bound on the number of selected entries.
3230 However each entry is indexed by it's enum so there can be holes in
3231 the table. */
3232 const CGEN_HW_ENTRY **selected =
3233 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
3234
3235 cd->hw_table.init_entries = init;
3236 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
3237 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
3238 /* ??? For now we just use machs to determine which ones we want. */
3239 for (i = 0; init[i].name != NULL; ++i)
3240 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
3241 & machs)
3242 selected[init[i].type] = &init[i];
3243 cd->hw_table.entries = selected;
3244 cd->hw_table.num_entries = MAX_HW;
3245 }
3246
3247 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */
3248
3249 static void
build_ifield_table(CGEN_CPU_TABLE * cd)3250 build_ifield_table (CGEN_CPU_TABLE *cd)
3251 {
3252 cd->ifld_table = & xc16x_cgen_ifld_table[0];
3253 }
3254
3255 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */
3256
3257 static void
build_operand_table(CGEN_CPU_TABLE * cd)3258 build_operand_table (CGEN_CPU_TABLE *cd)
3259 {
3260 int i;
3261 int machs = cd->machs;
3262 const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
3263 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
3264 However each entry is indexed by it's enum so there can be holes in
3265 the table. */
3266 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
3267
3268 cd->operand_table.init_entries = init;
3269 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
3270 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
3271 /* ??? For now we just use mach to determine which ones we want. */
3272 for (i = 0; init[i].name != NULL; ++i)
3273 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
3274 & machs)
3275 selected[init[i].type] = &init[i];
3276 cd->operand_table.entries = selected;
3277 cd->operand_table.num_entries = MAX_OPERANDS;
3278 }
3279
3280 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.
3281 ??? This could leave out insns not supported by the specified mach/isa,
3282 but that would cause errors like "foo only supported by bar" to become
3283 "unknown insn", so for now we include all insns and require the app to
3284 do the checking later.
3285 ??? On the other hand, parsing of such insns may require their hardware or
3286 operand elements to be in the table [which they mightn't be]. */
3287
3288 static void
build_insn_table(CGEN_CPU_TABLE * cd)3289 build_insn_table (CGEN_CPU_TABLE *cd)
3290 {
3291 int i;
3292 const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
3293 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
3294
3295 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
3296 for (i = 0; i < MAX_INSNS; ++i)
3297 insns[i].base = &ib[i];
3298 cd->insn_table.init_entries = insns;
3299 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
3300 cd->insn_table.num_init_entries = MAX_INSNS;
3301 }
3302
3303 /* Subroutine of xc16x_cgen_cpu_open to rebuild the tables. */
3304
3305 static void
xc16x_cgen_rebuild_tables(CGEN_CPU_TABLE * cd)3306 xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
3307 {
3308 int i;
3309 CGEN_BITSET *isas = cd->isas;
3310 unsigned int machs = cd->machs;
3311
3312 cd->int_insn_p = CGEN_INT_INSN_P;
3313
3314 /* Data derived from the isa spec. */
3315 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
3316 cd->default_insn_bitsize = UNSET;
3317 cd->base_insn_bitsize = UNSET;
3318 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
3319 cd->max_insn_bitsize = 0;
3320 for (i = 0; i < MAX_ISAS; ++i)
3321 if (cgen_bitset_contains (isas, i))
3322 {
3323 const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];
3324
3325 /* Default insn sizes of all selected isas must be
3326 equal or we set the result to 0, meaning "unknown". */
3327 if (cd->default_insn_bitsize == UNSET)
3328 cd->default_insn_bitsize = isa->default_insn_bitsize;
3329 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
3330 ; /* This is ok. */
3331 else
3332 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
3333
3334 /* Base insn sizes of all selected isas must be equal
3335 or we set the result to 0, meaning "unknown". */
3336 if (cd->base_insn_bitsize == UNSET)
3337 cd->base_insn_bitsize = isa->base_insn_bitsize;
3338 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
3339 ; /* This is ok. */
3340 else
3341 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
3342
3343 /* Set min,max insn sizes. */
3344 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
3345 cd->min_insn_bitsize = isa->min_insn_bitsize;
3346 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
3347 cd->max_insn_bitsize = isa->max_insn_bitsize;
3348 }
3349
3350 /* Data derived from the mach spec. */
3351 for (i = 0; i < MAX_MACHS; ++i)
3352 if (((1 << i) & machs) != 0)
3353 {
3354 const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];
3355
3356 if (mach->insn_chunk_bitsize != 0)
3357 {
3358 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
3359 {
3360 fprintf (stderr, "xc16x_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
3361 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
3362 abort ();
3363 }
3364
3365 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
3366 }
3367 }
3368
3369 /* Determine which hw elements are used by MACH. */
3370 build_hw_table (cd);
3371
3372 /* Build the ifield table. */
3373 build_ifield_table (cd);
3374
3375 /* Determine which operands are used by MACH/ISA. */
3376 build_operand_table (cd);
3377
3378 /* Build the instruction table. */
3379 build_insn_table (cd);
3380 }
3381
3382 /* Initialize a cpu table and return a descriptor.
3383 It's much like opening a file, and must be the first function called.
3384 The arguments are a set of (type/value) pairs, terminated with
3385 CGEN_CPU_OPEN_END.
3386
3387 Currently supported values:
3388 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
3389 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
3390 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
3391 CGEN_CPU_OPEN_ENDIAN: specify endian choice
3392 CGEN_CPU_OPEN_END: terminates arguments
3393
3394 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
3395 precluded.
3396
3397 ??? We only support ISO C stdargs here, not K&R.
3398 Laziness, plus experiment to see if anything requires K&R - eventually
3399 K&R will no longer be supported - e.g. GDB is currently trying this. */
3400
3401 CGEN_CPU_DESC
xc16x_cgen_cpu_open(enum cgen_cpu_open_arg arg_type,...)3402 xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
3403 {
3404 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
3405 static int init_p;
3406 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
3407 unsigned int machs = 0; /* 0 = "unspecified" */
3408 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
3409 va_list ap;
3410
3411 if (! init_p)
3412 {
3413 init_tables ();
3414 init_p = 1;
3415 }
3416
3417 memset (cd, 0, sizeof (*cd));
3418
3419 va_start (ap, arg_type);
3420 while (arg_type != CGEN_CPU_OPEN_END)
3421 {
3422 switch (arg_type)
3423 {
3424 case CGEN_CPU_OPEN_ISAS :
3425 isas = va_arg (ap, CGEN_BITSET *);
3426 break;
3427 case CGEN_CPU_OPEN_MACHS :
3428 machs = va_arg (ap, unsigned int);
3429 break;
3430 case CGEN_CPU_OPEN_BFDMACH :
3431 {
3432 const char *name = va_arg (ap, const char *);
3433 const CGEN_MACH *mach =
3434 lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);
3435
3436 machs |= 1 << mach->num;
3437 break;
3438 }
3439 case CGEN_CPU_OPEN_ENDIAN :
3440 endian = va_arg (ap, enum cgen_endian);
3441 break;
3442 default :
3443 fprintf (stderr, "xc16x_cgen_cpu_open: unsupported argument `%d'\n",
3444 arg_type);
3445 abort (); /* ??? return NULL? */
3446 }
3447 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
3448 }
3449 va_end (ap);
3450
3451 /* Mach unspecified means "all". */
3452 if (machs == 0)
3453 machs = (1 << MAX_MACHS) - 1;
3454 /* Base mach is always selected. */
3455 machs |= 1;
3456 if (endian == CGEN_ENDIAN_UNKNOWN)
3457 {
3458 /* ??? If target has only one, could have a default. */
3459 fprintf (stderr, "xc16x_cgen_cpu_open: no endianness specified\n");
3460 abort ();
3461 }
3462
3463 cd->isas = cgen_bitset_copy (isas);
3464 cd->machs = machs;
3465 cd->endian = endian;
3466 /* FIXME: for the sparc case we can determine insn-endianness statically.
3467 The worry here is where both data and insn endian can be independently
3468 chosen, in which case this function will need another argument.
3469 Actually, will want to allow for more arguments in the future anyway. */
3470 cd->insn_endian = endian;
3471
3472 /* Table (re)builder. */
3473 cd->rebuild_tables = xc16x_cgen_rebuild_tables;
3474 xc16x_cgen_rebuild_tables (cd);
3475
3476 /* Default to not allowing signed overflow. */
3477 cd->signed_overflow_ok_p = 0;
3478
3479 return (CGEN_CPU_DESC) cd;
3480 }
3481
3482 /* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
3483 MACH_NAME is the bfd name of the mach. */
3484
3485 CGEN_CPU_DESC
xc16x_cgen_cpu_open_1(const char * mach_name,enum cgen_endian endian)3486 xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
3487 {
3488 return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
3489 CGEN_CPU_OPEN_ENDIAN, endian,
3490 CGEN_CPU_OPEN_END);
3491 }
3492
3493 /* Close a cpu table.
3494 ??? This can live in a machine independent file, but there's currently
3495 no place to put this file (there's no libcgen). libopcodes is the wrong
3496 place as some simulator ports use this but they don't use libopcodes. */
3497
3498 void
xc16x_cgen_cpu_close(CGEN_CPU_DESC cd)3499 xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
3500 {
3501 unsigned int i;
3502 const CGEN_INSN *insns;
3503
3504 if (cd->macro_insn_table.init_entries)
3505 {
3506 insns = cd->macro_insn_table.init_entries;
3507 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
3508 if (CGEN_INSN_RX ((insns)))
3509 regfree (CGEN_INSN_RX (insns));
3510 }
3511
3512 if (cd->insn_table.init_entries)
3513 {
3514 insns = cd->insn_table.init_entries;
3515 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
3516 if (CGEN_INSN_RX (insns))
3517 regfree (CGEN_INSN_RX (insns));
3518 }
3519
3520 if (cd->macro_insn_table.init_entries)
3521 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
3522
3523 if (cd->insn_table.init_entries)
3524 free ((CGEN_INSN *) cd->insn_table.init_entries);
3525
3526 if (cd->hw_table.entries)
3527 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
3528
3529 if (cd->operand_table.entries)
3530 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
3531
3532 free (cd);
3533 }
3534
3535