1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY 11 * 12 * @(#)adrsmap.h 8.1 (Berkeley) 06/11/93 13 */ 14 15 /* 16 * adrsmap.h 17 * 18 * Define all hardware address map. 19 */ 20 21 #ifndef __ADRSMAP__ 22 #define __ADRSMAP__ 1 23 24 #ifdef news3400 25 /*---------------------------------------------------------------------- 26 * news3400 27 *----------------------------------------------------------------------*/ 28 /* 29 * timer 30 */ 31 #define RTC_PORT 0xbff407f8 32 #define DATA_PORT 0xbff407f9 33 34 #ifdef notdef 35 #define EN_ITIMER 0xb8000004 /*XXX:???*/ 36 #endif 37 38 #define INTEN0 0xbfc80000 39 #define INTEN0_PERR 0x80 40 #define INTEN0_ABORT 0x40 41 #define INTEN0_BERR 0x20 42 #define INTEN0_TIMINT 0x10 43 #define INTEN0_KBDINT 0x08 44 #define INTEN0_MSINT 0x04 45 #define INTEN0_CFLT 0x02 46 #define INTEN0_CBSY 0x01 47 48 #define INTEN1 0xbfc80001 49 #define INTEN1_BEEP 0x80 50 #define INTEN1_SCC 0x40 51 #define INTEN1_LANCE 0x20 52 #define INTEN1_DMA 0x10 53 #define INTEN1_SLOT1 0x08 54 #define INTEN1_SLOT3 0x04 55 #define INTEN1_EXT1 0x02 56 #define INTEN1_EXT3 0x01 57 58 #define INTST0 0xbfc80002 59 #define INTST0_PERR 0x80 60 #define INTST0_ABORT 0x40 61 #define INTST0_BERR 0x00 /* N/A */ 62 #define INTST0_TIMINT 0x10 63 #define INTST0_KBDINT 0x08 64 #define INTST0_MSINT 0x04 65 #define INTST0_CFLT 0x02 66 #define INTST0_CBSY 0x01 67 #define INTST0_PERR_BIT 7 68 #define INTST0_ABORT_BIT 6 69 #define INTST0_BERR_BIT 5 /* N/A */ 70 #define INTST0_TIMINT_BIT 4 71 #define INTST0_KBDINT_BIT 3 72 #define INTST0_MSINT_BIT 2 73 #define INTST0_CFLT_BIT 1 74 #define INTST0_CBSY_BIT 0 75 76 #define INTST1 0xbfc80003 77 #define INTST1_BEEP 0x80 78 #define INTST1_SCC 0x40 79 #define INTST1_LANCE 0x20 80 #define INTST1_DMA 0x10 81 #define INTST1_SLOT1 0x08 82 #define INTST1_SLOT3 0x04 83 #define INTST1_EXT1 0x02 84 #define INTST1_EXT3 0x01 85 #define INTST1_BEEP_BIT 7 86 #define INTST1_SCC_BIT 6 87 #define INTST1_LANCE_BIT 5 88 #define INTST1_DMA_BIT 4 89 #define INTST1_SLOT1_BIT 3 90 #define INTST1_SLOT3_BIT 2 91 #define INTST1_EXT1_BIT 1 92 #define INTST1_EXT3_BIT 0 93 94 #define INTCLR0 0xbfc80004 95 #define INTCLR0_PERR 0x80 96 #define INTCLR0_ABORT 0x40 97 #define INTCLR0_BERR 0x20 98 #define INTCLR0_TIMINT 0x10 99 #define INTCLR0_KBDINT 0x00 /* N/A */ 100 #define INTCLR0_MSINT 0x00 /* N/A */ 101 #define INTCLR0_CFLT 0x02 102 #define INTCLR0_CBSY 0x01 103 104 #define INTCLR1 0xbfc80005 105 #define INTCLR1_BEEP 0x80 106 #define INTCLR1_SCC 0x00 /* N/A */ 107 #define INTCLR1_LANCE 0x00 /* N/A */ 108 #define INTCLR1_DMA 0x00 /* N/A */ 109 #define INTCLR1_SLOT1 0x00 /* N/A */ 110 #define INTCLR1_SLOT3 0x00 /* N/A */ 111 #define INTCLR1_EXT1 0x00 /* N/A */ 112 #define INTCLR1_EXT3 0x00 /* N/A */ 113 114 #define ITIMER 0xbfc80006 115 #define IOCLOCK 4915200 116 117 #define DIP_SWITCH 0xbfe40000 118 #define IDROM 0xbfe80000 119 120 #define DEBUG_PORT 0xbfcc0003 121 #define DP_READ 0x00 122 #define DP_WRITE 0xf0 123 #define DP_LED0 0x01 124 #define DP_LED1 0x02 125 #define DP_LED2 0x04 126 #define DP_LED3 0x08 127 128 129 #define LANCE_PORT 0xbff80000 130 #define LANCE_MEMORY 0xbffc0000 131 #define ETHER_ID IDROM_PORT 132 133 #define LANCE_PORT1 0xb8c30000 /* expansion lance #1 */ 134 #define LANCE_MEMORY1 0xb8c20000 135 #define ETHER_ID1 0xb8c38000 136 137 #define LANCE_PORT2 0xb8c70000 /* expansion lance #2 */ 138 #define LANCE_MEMORY2 0xb8c60000 139 #define ETHER_ID2 0xb8c78000 140 141 #define IDROM_PORT 0xbfe80000 142 143 #define SCCPORT0B 0xbfec0000 144 #define SCCPORT0A 0xbfec0002 145 #define SCCPORT1B 0xb8c40100 146 #define SCCPORT1A 0xb8c40102 147 #define SCCPORT2B 0xb8c40104 148 #define SCCPORT2A 0xb8c40106 149 #define SCCPORT3B 0xb8c40110 150 #define SCCPORT3A 0xb8c40112 151 #define SCCPORT4B 0xb8c40114 152 #define SCCPORT4A 0xb8c40116 153 154 #define SCC_STATUS0 0xbfcc0002 155 #define SCC_STATUS1 0xb8c40108 156 #define SCC_STATUS2 0xb8c40118 157 158 #define SCCVECT (0x1fcc0007 | MACH_UNCACHED_MEMORY_ADDR) 159 #define SCC_RECV 2 160 #define SCC_XMIT 0 161 #define SCC_CTRL 3 162 #define SCC_STAT 1 163 #define SCC_INT_MASK 0x6 164 165 /*XXX: SHOULD BE FIX*/ 166 #define KEYB_DATA 0xbfd00000 /* keyboard data port */ 167 #define KEYB_STAT 0xbfd00001 /* keyboard status port */ 168 #define KEYB_INTE INTEN0 /* keyboard interrupt enable */ 169 #define KEYB_RESET 0xbfd00002 /* keyboard reset port*/ 170 #define KEYB_INIT1 0xbfd00003 /* keyboard speed */ 171 #define KEYB_INIT2 KEYB_INIT1 /* keyboard clock */ 172 #define KEYB_BUZZ 0xbfd40001 /* keyboard buzzer (length) */ 173 #define KEYB_BUZZF 0xbfd40000 /* keyboard buzzer frequency */ 174 #define MOUSE_DATA 0xbfd00004 /* mouse data port */ 175 #define MOUSE_STAT 0xbfd00005 /* mouse status port */ 176 #define MOUSE_INTE INTEN0 /* mouse interrupt enable */ 177 #define MOUSE_RESET 0xbfd00006 /* mouse reset port */ 178 #define MOUSE_INIT1 0xbfd00007 /* mouse speed */ 179 #define MOUSE_INIT2 MOUSE_INIT1 /* mouse clock */ 180 181 #define RX_MSINTE 0x04 /* Mouse Interrupt Enable */ 182 #define RX_KBINTE 0x08 /* Keyboard Intr. Enable */ 183 #define RX_MSINT 0x04 /* Mouse Interrupted */ 184 #define RX_KBINT 0x08 /* Keyboard Interrupted */ 185 #define RX_MSBUF 0x01 /* Mouse data buffer Full */ 186 #define RX_KBBUF 0x01 /* Keyboard data Full */ 187 #define RX_MSRDY 0x02 /* Mouse data ready */ 188 #define RX_KBRDY 0x02 /* Keyboard data ready */ 189 /*XXX: SHOULD BE FIX*/ 190 191 #define ABEINT_BADDR 0xbfdc0038 192 #endif /* news3400 */ 193 194 #endif /* !__ADRSMAP__ */ 195