Home
last modified time | relevance | path

Searched refs:CP0SC_PA (Results 1 – 2 of 2) sorted by relevance

/qemu/target/mips/
H A Dcpu.c366 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | in mips_cpu_reset_hold()
369 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | in mips_cpu_reset_hold()
372 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | in mips_cpu_reset_hold()
375 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | in mips_cpu_reset_hold()
H A Dcpu.h635 #define CP0SC_PA 9 macro
636 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
637 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)