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Searched refs:CP0_REG18__WATCHLO5 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/mips/
H A Dcpu.h392 #define CP0_REG18__WATCHLO5 5 macro
/qemu/target/mips/tcg/
H A Dtranslate.c5599 case CP0_REG18__WATCHLO5: in gen_mfc0()
6333 case CP0_REG18__WATCHLO5: in gen_mtc0()
7075 case CP0_REG18__WATCHLO5: in gen_dmfc0()
7794 case CP0_REG18__WATCHLO5: in gen_dmtc0()