/qemu/target/hexagon/ |
H A D | macros.h | 105 #define MEM_LOAD1s(DST, VA) \ 110 #define MEM_LOAD1u(DST, VA) \ 115 #define MEM_LOAD2s(DST, VA) \ 120 #define MEM_LOAD2u(DST, VA) \ 285 DST = __sum; \ 296 DST = __sum; \ 518 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) 576 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ 589 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ 602 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ [all …]
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/qemu/scripts/ |
H A D | entitlement.sh | 11 DST="$1" 18 cp -pPf "$SRC" "$DST.tmp" 19 SRC="$DST.tmp" 32 mv -f "$SRC" "$DST"
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/qemu/target/hexagon/imported/ |
H A D | macros.def | 236 DST = __sum; 248 DST = __sum; 1106 DST = fSFNANVAL(); 1115 fCHECKSFNAN(DST,A); 1116 fCHECKSFNAN(DST,B); 1117 fCHECKSFNAN(DST,C); 1398 DST = (DST & ~(0x0ffLL<<((N)*8))) | (((size8u_t)((VAL) & 0x0ffLL)) << ((N)*8)); 1415 DST = (DST & ~(0x0ffffLL<<((N)*16))) | (((size8u_t)((VAL) & 0x0ffff)) << ((N)*16)); 1434 DST = (DST & ~(0x0ffffffffLL<<((N)*32))) | (((VAL) & 0x0ffffffffLL) << ((N)*32)); 1441 DST = (DST & ~(1ULL<<(N))) | (((size8u_t)(VAL))<<(N)); [all …]
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H A D | mpy.idef | 23 #define STD_SP_MODES(TAG,OPER,ATR,DST,ACCSEM,SEM,OSEM,SATSEM,RNDSEM)\ 24 Q6INSN(M2_##TAG##_hh_s0, OPER"(Rs.H32,Rt.H32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( … 25 Q6INSN(M2_##TAG##_hh_s1, OPER"(Rs.H32,Rt.H32):<<1"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM fSCALE(… 26 Q6INSN(M2_##TAG##_hl_s0, OPER"(Rs.H32,Rt.L32)"OSEM, ATR,"",{DST=SATSEM(RNDSEM(ACCSEM SEM( … 53 #define STD_USP_MODES(TAG,OPER,ATR,DST,ACCSEM,SEM,OSEM,SATSEM,RNDSEM)\ 916 #define VCMPYSEMI(DST,ACC0,ACC1,SHIFT,SAT) \ 917 fSETWORD(0,DST,SAT(ACC0 fSCALE(SHIFT,fMPY16SS(fGETHALF(1,RssV),fGETHALF(0,RttV)) + \ 919 fSETWORD(1,DST,SAT(ACC1 fSCALE(SHIFT,fMPY16SS(fGETHALF(3,RssV),fGETHALF(2,RttV)) + \ 923 #define VCMPYSEMR(DST,ACC0,ACC1,SHIFT,SAT) \ 924 fSETWORD(0,DST,SAT(ACC0 fSCALE(SHIFT,fMPY16SS(fGETHALF(0,RssV),fGETHALF(0,RttV)) - \ [all …]
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H A D | alu.idef | 1129 #define CROUND(DST,SRC,SHIFT) \ 1134 DST = SRC;\ 1143 DST = fCAST16S_8S(tmp128);\ 1149 DST = fCAST16S_8S(tmp128);\
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/qemu/target/alpha/ |
H A D | helper.c | 30 #define CONVERT_BIT(X, SRC, DST) \ argument 31 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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H A D | fpu_helper.c | 39 #define CONVERT_BIT(X, SRC, DST) \ argument 40 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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/qemu/target/hexagon/imported/mmvec/ |
H A D | macros.def | 523 …mem_load_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &DST.ub[0], LEN, fUSE_… 529 fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST), 536 fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST); 537 fVFOREACH(8,__i) if (!fGETQBIT(QVAL,__i)) DST.b[__i] = 0; 545 fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST); 546 fVFOREACH(8,__i) if (fGETQBIT(QVAL,__i)) DST.b[__i] = 0; 556 …mem_load_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &DST.ub[size1], … 557 …mem_load_vector_oddva(thread, insn, EA, EA,/* slot */ 0, size1, &DST.ub[0], size1, fUSE_LOOKUP_ADD… 571 fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST); 576 fLOADMMVU_AL(EA,fVECSIZE(),fVECSIZE(),DST);
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/qemu/target/hppa/ |
H A D | fpu_helper.c | 59 #define CONVERT_BIT(X, SRC, DST) \ argument 60 ((unsigned)(SRC) > (unsigned)(DST) \ 61 ? (X) / ((SRC) / (DST)) & (DST) \ 62 : ((X) & (SRC)) * ((DST) / (SRC)))
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/qemu/target/sparc/ |
H A D | cpu.h | 361 #define CONVERT_BIT(X, SRC, DST) \ argument 362 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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/qemu/target/arm/ |
H A D | cpu.h | 3192 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ argument 3193 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3194 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ argument 3195 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3196 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ argument 3197 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3198 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ argument 3199 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3200 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ argument 3201 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
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/qemu/target/hexagon/mmvec/ |
H A D | macros.h | 283 #define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_off, EA, true) 286 #define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_off, EA, false)
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/qemu/target/hexagon/idef-parser/ |
H A D | macros.h.inc | 40 #define fCLIP(DST, SRC, U) (DST = fMIN((1 << U) - 1, fMAX(SRC, -(1 << U))))
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/qemu/target/loongarch/ |
H A D | cpu-csr.h | 202 FIELD(CSR_DBG, DST, 0, 1)
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H A D | cpu.c | 144 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); in cpu_loongarch_hw_interrupts_enabled() 188 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); in loongarch_cpu_do_interrupt() 192 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { in loongarch_cpu_do_interrupt()
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/qemu/target/loongarch/tcg/ |
H A D | tlb_helper.c | 109 if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { in raise_mmu_exception()
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/qemu/target/i386/tcg/ |
H A D | emit.c.inc | 1258 /* Compute adjusted DST in T1, merging in SRC[RPL]. */ 1261 /* Z flag set if DST[RPL] < SRC[RPL] */ 1265 /* Place maximum RPL in DST */
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