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Searched refs:MSR_WE (Results 1 – 2 of 2) sorted by relevance

/qemu/target/ppc/
H A Dcpu.h439 #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */ macro
489 FIELD(MSR, WE, MSR_WE, 1)
H A Dcpu_init.c2173 pcc->msr_mask = (1ull << MSR_WE) |