Searched refs:OPC_REGIMM (Results 1 – 2 of 2) sorted by relevance
| /qemu/target/mips/tcg/ |
| H A D | translate.c | 55 OPC_REGIMM = (0x01 << 26), enumerator
299 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
300 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
301 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
302 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
303 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
304 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
305 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
306 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
307 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
[all …]
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| /qemu/tcg/mips/ |
| H A D | tcg-target.c.inc | 319 OPC_REGIMM = 001 << 26,
320 OPC_BLTZ = OPC_REGIMM | (000 << 16),
321 OPC_BGEZ = OPC_REGIMM | (001 << 16),
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