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Searched refs:RsV (Results 1 – 17 of 17) sorted by relevance

/qemu/target/hexagon/
H A Darch.c246 RsV = *Rs; in arch_sf_recip_common()
284 RsV = make_float32(0x80000000 & (RsV ^ RtV)); in arch_sf_recip_common()
290 RsV = make_float32(0x80000000 & (RsV ^ RtV)); in arch_sf_recip_common()
308 RsV = float32_scalbn(RsV, 64, fp_status); in arch_sf_recip_common()
313 RsV = float32_scalbn(RsV, -32, fp_status); in arch_sf_recip_common()
316 RsV = float32_scalbn(RsV, 64, fp_status); in arch_sf_recip_common()
319 RsV = float32_scalbn(RsV, 32, fp_status); in arch_sf_recip_common()
322 RsV = float32_scalbn(RsV, -32, fp_status); in arch_sf_recip_common()
327 *Rs = RsV; in arch_sf_recip_common()
341 RsV = *Rs; in arch_sf_invsqrt_common()
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H A Dgen_tcg.h494 do { RsV = RsV; } while (0)
496 do { RsV = RsV; } while (0)
498 do { RsV = RsV; } while (0)
500 do { RsV = RsV; } while (0)
695 gen_callr(ctx, RsV)
697 gen_callr(ctx, RsV)
1327 RsV = RsV; \
1332 RsV = RsV; \
1342 RsV = RsV; \
1352 RsV = RsV; \
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H A Dop_helper.c348 idx = (RsV >> 17) & 0x7f; in HELPER()
686 if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) { in HELPER()
701 if (float32_is_any_nan(RsV)) { in HELPER()
716 if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) { in HELPER()
731 if (float32_is_any_nan(RsV)) { in HELPER()
806 if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) { in HELPER()
821 if (float32_is_any_nan(RsV)) { in HELPER()
836 if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) { in HELPER()
1028 RdV = RsV; in HELPER()
1050 RdV = RsV; in HELPER()
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H A Dgenptr.c546 static inline void gen_loop0r(DisasContext *ctx, TCGv RsV, int riV) in gen_loop0r() argument
550 gen_log_reg_write(ctx, HEX_REG_LC0, RsV); in gen_loop0r()
560 static inline void gen_loop1r(DisasContext *ctx, TCGv RsV, int riV) in gen_loop1r() argument
564 gen_log_reg_write(ctx, HEX_REG_LC1, RsV); in gen_loop1r()
573 static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV) in gen_ploopNsr() argument
577 gen_log_reg_write(ctx, HEX_REG_LC0, RsV); in gen_ploopNsr()
1055 gen_shl_sat(ctx, RdV, RsV, shift_amt); in gen_asr_r_r_sat()
1060 gen_sar(RdV, RsV, shift_amt); in gen_asr_r_r_sat()
1077 gen_sar(RdV, RsV, shift_amt); in gen_asl_r_r_sat()
1082 gen_shl_sat(ctx, RdV, RsV, shift_amt); in gen_asl_r_r_sat()
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H A DREADME63 Instruction semantics "{ RdV=RsV+RtV;}"
67 RsV, RtV are source registers
85 TCGv RsV = hex_gpr[insn->regno[1]];
87 gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
92 int32_t HELPER(A2_add)(CPUHexagonState *env, int32_t RsV, int32_t RtV)
96 { RdV=RsV+RtV;}
115 tcg_gen_add_tl(RdV, RsV, RtV)
123 Instruction semantics "{ fEA_REG(RsV); fLOAD_LOCKED(1,4,u,EA,RdV) }"
/qemu/target/hexagon/imported/
H A Dfloat.idef27 { RdV=fUNFLOAT(fFLOAT(RsV)+fFLOAT(RtV));})
31 { RdV=fUNFLOAT(fFLOAT(RsV)-fFLOAT(RtV));})
45 fCHECKSFNAN3(RxV,RxV,RsV,RtV);
61 fCHECKSFNAN3(RxV,RxV,RsV,RtV);
76 fCHECKSFNAN3(RxV,RxV,RsV,RtV);
91 {PdV=f8BITSOF(fFLOAT(RsV)>fFLOAT(RtV));})
120 class = fpclassify(fFLOAT(RsV));
170 RdV = RsV;
190 idx = (RsV >> 17) & 0x7f;
201 fSF_INVSQRT_COMMON(RsV,RdV,adjust);
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H A Dbranch.idef35 {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);})
38 {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);})
50 fJUMPR(RsN,RsV,COF_TYPE_JUMPR);)
62 fJUMPR(RsN,RsV,COF_TYPE_JUMPR);)
67 {fHINTJR(RsV);})
80 {fBRANCH_SPECULATE_STALL((RsV!=0), , SPECULATE_TAKEN,12,0) if (RsV != 0) { fBRANCH(fREAD_PC()+riV,C…
83 {fBRANCH_SPECULATE_STALL((RsV==0), , SPECULATE_TAKEN,12,0) if (RsV == 0) {fBRANCH(fREAD_PC()+riV,CO…
89 {fBRANCH_SPECULATE_STALL((RsV>=0), , SPECULATE_TAKEN,12,0) if (RsV>=0) { fBRANCH(fREAD_PC()+riV,COF…
95 {fBRANCH_SPECULATE_STALL((RsV<=0), , SPECULATE_TAKEN,12,0) if (RsV<=0) { fBRANCH(fREAD_PC()+riV,COF…
194 { fCALLR(RsV); })
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H A Dalu.idef29 { RdV=RsV+RtV;})
33 { RdV=RtV-RsV;})
204 { RdV = fMAX(RsV,RtV); })
269 fSETWORD(1,RddV,RsV);
275 fSETWORD(1,RddV,RsV);
472 { RdV = fSATH(RsV); })
476 { RdV = fSATUH(RsV); })
480 { RdV = fSATUB(RsV); })
484 { RdV = fSATB(RsV); })
1295 if (RsV < 0) {
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H A Dcompare.idef30 {PdV=f8BITSOF(RsV==RtV);})
34 {PdV=f8BITSOF(RsV>RtV);})
71 {RdV=(RsV==RtV); })
75 {RdV=(RsV!=RtV); })
90 {PdV=f8BITSOF((RsV&RtV)==0);})
99 {PdV=f8BITSOF((RsV&RtV)!=0);})
121 {PdV=f8BITSOF((RsV&uiV)==0);})
240 fSETWORD(1,RddV,RsV);
248 fSETWORD(1,RddV,RsV);
256 fSETWORD(1,RddV,RsV);
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H A Dmpy.idef76 { fIMMEXT(uiV); RdV=RsV*uiV; })
80 { RdV=RsV*-uiV; })
123 { RdV=RsV*RtV;})
127 { RxV=RxV + RsV*RtV;})
131 { RxV=RxV - RsV*RtV;})
137 { RxV=RxV + RsV + RtV;})
145 { RxV=RxV - (RsV + RtV);})
153 { RxV=RxV + RtV - RsV;})
160 { RyV = RuV + RsV*RyV;})
164 { RdV = RuV + RsV*uiV;})
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H A Dsubinsns.idef31 Q6INSN(SA1_tfr, "Rd16=Rs16", ATTRIBS(A_SUBINSN),"Tfr", { RdV=RsV;})
40 Q6INSN(SA1_inc, "Rd16=add(Rs16,#1)", ATTRIBS(A_SUBINSN),"Inc", { RdV=RsV+1;})
41 Q6INSN(SA1_dec, "Rd16=add(Rs16,#-1)", ATTRIBS(A_SUBINSN),"Dec", { RdV=RsV-1;})
42 …A1_addrx, "Rx16=add(Rx16,Rs16)", ATTRIBS(A_SUBINSN,A_COMMUTES),"Add", { RxV=RxV+RsV; })
43 …N(SA1_zxtb, "Rd16=and(Rs16,#255)", ATTRIBS(A_SUBINSN),"Zxtb", { RdV= fZXTN(8,32,RsV);})
44 Q6INSN(SA1_and1, "Rd16=and(Rs16,#1)", ATTRIBS(A_SUBINSN),"And #1", { RdV= RsV&1;})
45 …N(SA1_sxtb, "Rd16=sxtb(Rs16)", ATTRIBS(A_SUBINSN),"Sxtb", { RdV= fSXTN(8,32,RsV);})
46 …(SA1_zxth, "Rd16=zxth(Rs16)", ATTRIBS(A_SUBINSN),"Zxth", { RdV= fZXTN(16,32,RsV);})
47 …(SA1_sxth, "Rd16=sxth(Rs16)", ATTRIBS(A_SUBINSN),"Sxth", { RdV= fSXTN(16,32,RsV);})
48 …ine(#0,Rs16)", ATTRIBS(A_SUBINSN,A_ROPS_2),"Combines", { fSETWORD(0,RddV,RsV); fSETWORD(1,RddV,0…
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H A Dsystem.idef36 …)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",{fEA_REG(RsV); fICINVA(EA);})
43 …)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);…
46 …,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);})
47 …TTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Address",{fEA_REG(RsV); fDCCLEANA(EA);})
48 …_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean and Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);…
49 …A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);…
53 { fL2FETCH(RsV,
63 { fL2FETCH(RsV,
H A Dshift.idef464 RdV = (RsV | (1<<uiV));
470 RdV = (RsV ^ (1<<uiV));
476 RdV = (RsV & (~(1<<uiV)));
900 fSETHALF(1,RddV,fGETHALF(0,RsV));
908 fSETBYTE(0,RdV,fGETBYTE(3,RsV));
909 fSETBYTE(1,RdV,fGETBYTE(2,RsV));
910 fSETBYTE(2,RdV,fGETBYTE(1,RsV));
911 fSETBYTE(3,RdV,fGETBYTE(0,RsV));
1017 "Count leading sign bits - 1", { if (RsV == 0) { RdV = 0; } else { RdV = (fMAX(fCL1_4(RsV),fCL1_4(~…
1021 { RdV = (fMAX(fCL1_4(RsV),fCL1_4(~RsV)))+siV;} )
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H A Dldst.idef136 { fEA_REG(RsV); fLOAD(1,4,u,EA,RdV); })
138 { fEA_REG(RsV); fLOAD(1,8,u,EA,RddV); })
140 …AD,A_RESTRICT_NOPACKET,A_RESTRICT_SLOT0ONLY), "Release lock", {fEA_REG(RsV); fSTORE(1,0,EA,RsV); })
150 { fHIDE(size8u_t tmp;) fEA_REG(RsV);
156 { fHIDE(size8u_t tmp;) fEA_REG(RsV);
179 CONDSEM(RsV,STALLBITS0,STALLBITS1,PREDFUNC,PREDARG,STALLSPEC,)) \
181 CONDSEM(RsV,STALLBITS0,STALLBITS1,PREDFUNC##NOT,PREDARG,STALLSPEC,))
196 { fEA_REG(RsV); fLOAD_LOCKED(1,4,u,EA,RdV) })
200 { fEA_REG(RsV); fSTORE_LOCKED(1,4,EA,RtV,PdV) })
204 { fEA_REG(RsV); fLOAD_LOCKED(1,8,u,EA,RddV) })
[all …]
/qemu/target/hexagon/idef-parser/
H A DREADME.rst19 { RdV=RsV+RtV;}
29 /* { RdV=RsV+RtV;} */
66 { RdV=RsV+RtV;}
134 J2_jumpr(in RsV) {
150 J2_jumpr(in RsV) {
151 {(PC = RsV);}
154 where ``fJUMPR(RsN,RsV,COF_TYPE_JUMPR);`` was expanded to ``(PC = RsV)``,
515 /* RdV=RsV+RtV;} */
518 tcg_gen_add_i32(tmp_0, RsV, RsV);
522 Here the bug, albeit hard to spot, is in ``tcg_gen_add_i32(tmp_0, RsV, RsV);``
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H A Didef-parser.lex472 "fHINTJR(RsV)" { /* Emit no token */ }
/qemu/target/hexagon/imported/mmvec/
H A Dext.idef2036 fHIDE(warn("RdN=%d VuN=%d RsN=%d RsV=0x%08x widx=%d",RdN,VuN,RsN,RsV,((RsV & (fVBYTES()-1)) >> 2));)
2037 RdV = VuV.uw[ (RsV & (fVBYTES()-1)) >> 2];