| /qemu/hw/ssi/ |
| H A D | pnv_spi.c | 462 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); in operation_shiftn1()
478 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 1); in operation_shiftn1()
668 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); in operation_shiftn2()
719 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 0); in operation_sequencer()
725 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); in operation_sequencer()
1003 s->status = SETFIELD(SPI_STS_SEQ_INDEX, in operation_sequencer()
1098 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); in pnv_spi_xscom_read()
1162 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 1); in pnv_spi_xscom_write()
1163 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 0); in pnv_spi_xscom_write()
1174 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, in pnv_spi_xscom_write()
[all …]
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| /qemu/tests/qtest/ |
| H A D | pnv-host-i2c-test.c | 24 #define SETFIELD(m, v, val) \ macro
68 reg64 = SETFIELD(I2C_MODE_BIT_RATE_DIV, 0ull, 0x2be); in pnv_i2c_send()
69 reg64 = SETFIELD(I2C_MODE_PORT_NUM, reg64, dev->port); in pnv_i2c_send()
81 reg64 = SETFIELD(I2C_CMD_DEV_ADDR, reg64, dev->addr); in pnv_i2c_send()
82 reg64 = SETFIELD(I2C_CMD_LEN_BYTES, reg64, len); in pnv_i2c_send()
91 reg64 = SETFIELD(I2C_FIFO, 0ull, buf[byte_num]); in pnv_i2c_send()
110 reg64 = SETFIELD(I2C_MODE_BIT_RATE_DIV, 0ull, 0x2be); in pnv_i2c_recv()
111 reg64 = SETFIELD(I2C_MODE_PORT_NUM, reg64, dev->port); in pnv_i2c_recv()
124 reg64 = SETFIELD(I2C_CMD_DEV_ADDR, reg64, dev->addr); in pnv_i2c_recv()
125 reg64 = SETFIELD(I2C_CMD_LEN_BYTES, reg64, len); in pnv_i2c_recv()
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| /qemu/hw/ppc/ |
| H A D | pnv_i2c.c | 114 i2c->regs[I2C_STAT_REG] = SETFIELD(I2C_STAT_FIFO_ENTRY_COUNT, stat, in pnv_i2c_fifo_update_count()
124 SETFIELD(I2C_RESIDUAL_FRONT_END, residual_end, front_end - 1); in pnv_i2c_frontend_update()
192 SETFIELD(I2C_RESIDUAL_FRONT_END, 0ull, len_bytes) | in pnv_i2c_handle_cmd()
193 SETFIELD(I2C_RESIDUAL_BACK_END, 0ull, len_bytes); in pnv_i2c_handle_cmd()
217 SETFIELD(I2C_RESIDUAL_BACK_END, residual_end, back_end - 1); in pnv_i2c_backend_update()
286 i2c->regs[I2C_FIFO_REG] = SETFIELD(I2C_FIFO, 0ull, data); in pnv_i2c_fifo_out()
344 SETFIELD(I2C_STAT_UPPER_THRS, 0ull, i2c->num_busses - 1) | in pnv_i2c_reset()
348 SETFIELD(I2C_EXTD_STAT_FIFO_SIZE, 0ull, PNV_I2C_FIFO_SIZE) | in pnv_i2c_reset()
349 SETFIELD(I2C_EXTD_STAT_I2C_VERSION, 0ull, 23); /* last version */ in pnv_i2c_reset()
|
| /qemu/include/hw/ssi/ |
| H A D | pnv_spi_regs.h | 23 #define SETFIELD(m, v, val) \ macro
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| /qemu/hw/intc/ |
| H A D | pnv_xive2.c | 739 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, in pnv_xive2_stt_set_data()
2220 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); in pnv_xive2_reset()
2224 SETFIELD(VC_ENDC_CFG_CACHE_WATCH_ASSIGN, 0ull, 0b0111); in pnv_xive2_reset()
2226 SETFIELD(PC_NXC_PROC_CONFIG_WATCH_ASSIGN, 0ull, 0b0111); in pnv_xive2_reset()
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| H A D | pnv_xive.c | 749 SETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3], ++tsel_index); in pnv_xive_table_set_data()
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| /qemu/hw/pci-host/ |
| H A D | pnv_phb4.c | 315 adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index); in pnv_phb4_ioda_access()
758 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, in pnv_phb4_xscom_read()
810 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, in pnv_phb4_xscom_write()
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| H A D | pnv_phb3.c | 303 adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index); in pnv_phb3_ioda_access()
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| /qemu/target/ppc/ |
| H A D | cpu.h | 59 #define SETFIELD(m, v, val) \ macro
|