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Searched refs:T1 (Results 1 – 12 of 12) sorted by relevance

/qemu/include/exec/
H A Dhelper-info.c.inc25 #define DEF_HELPER_FLAGS_1(NAME, FLAGS, RET, T1) \
29 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
32 #define DEF_HELPER_FLAGS_2(NAME, FLAGS, RET, T1, T2) \
36 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
40 #define DEF_HELPER_FLAGS_3(NAME, FLAGS, RET, T1, T2, T3) \
44 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
48 #define DEF_HELPER_FLAGS_4(NAME, FLAGS, RET, T1, T2, T3, T4) \
52 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
57 #define DEF_HELPER_FLAGS_5(NAME, FLAGS, RET, T1, T2, T3, T4, T5) \
61 .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
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/qemu/target/i386/tcg/
H A Demit.c.inc1236 tcg_gen_ext32u_tl(s->T1, s->T1);
1538 tcg_gen_ext8u_tl(s->T1, s->T1);
2064 tcg_gen_ext16s_tl(s->T1, s->T1);
2127 tcg_gen_ext8s_tl(s->T1, s->T1);
2137 tcg_gen_ext16s_tl(s->T1, s->T1);
2150 tcg_gen_ext32s_tl(s->T1, s->T1);
2621 tcg_gen_ext8u_tl(s->T1, s->T1);
2631 tcg_gen_ext16u_tl(s->T1, s->T1);
2643 tcg_gen_ext32u_tl(s->T1, s->T1);
3829 tcg_gen_andi_tl(s->T1, s->T1, mask);
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H A Dtranslate.c134 TCGv T1; member
1243 gen_op_ld_v(s, ot, s->T1, s->A0); in gen_scas()
1244 tcg_gen_mov_tl(cpu_cc_src, s->T1); in gen_scas()
1257 gen_op_ld_v(s, ot, s->T1, s->A0); in gen_cmps()
1260 tcg_gen_mov_tl(cpu_cc_src, s->T1); in gen_cmps()
1454 tcg_gen_deposit_tl(s->T1, s->T0, s->T1, 16, 16); in gen_shiftd_rm_T1()
1484 tcg_gen_shl_tl(s->T1, s->T1, s->tmp4); in gen_shiftd_rm_T1()
1496 tcg_gen_shr_tl(s->T1, s->T1, s->tmp4); in gen_shiftd_rm_T1()
2054 tcg_gen_subi_tl(s->T1, s->T1, esp_addend + size * level); in gen_enter()
3293 tcg_gen_andi_tl(s->T1, s->T1, ~0xe); in gen_multi0F()
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H A Ddecode-new.c.inc211 * and s->T1.
2834 gen_load(s, &decode, 2, s->T1);
2843 gen_load(s, &decode, 2, s->T1);
/qemu/docs/system/
H A Dtarget-sparc64.rst7 (UltraSPARC PC-like machine), Sun4v (T1 PC-like machine), or generic
8 Niagara (T1) machine. The Sun4u emulator is mostly complete, being able
12 The Niagara T1 emulator makes use of firmware and OS binaries supplied
13 in the S10image/ directory of the OpenSPARC T1 project
/qemu/target/riscv/
H A Dvector_internals.h181 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
184 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
209 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
213 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
H A Dvcrypto_helper.c515 uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0; in vsha2c_64() local
521 e = d + T1; in vsha2c_64()
525 a = T1 + T2; in vsha2c_64()
527 T1 = h + sum1_64(e) + ch(e, f, g) + W1; in vsha2c_64()
532 e = d + T1; in vsha2c_64()
536 a = T1 + T2; in vsha2c_64()
555 e = d + T1; in vsha2c_32()
559 a = T1 + T2; in vsha2c_32()
561 T1 = h + sum1_32(e) + ch(e, f, g) + W1; in vsha2c_32()
566 e = d + T1; in vsha2c_32()
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H A Dvector_helper.c1694 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
1697 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
1740 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
2865 #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ in RVVCALL() argument
2869 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ in RVVCALL()
2911 #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
2916 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
3146 #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ in RVVCALL() argument
3150 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ in RVVCALL()
3178 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ in RVVCALL() argument
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/qemu/tcg/
H A Dtci.c381 uint64_t T1, T2; in tcg_qemu_tb_exec() local
459 T1 = tci_uint64(regs[r2], regs[r1]); in tcg_qemu_tb_exec()
461 regs[r0] = tci_compare64(T1, T2, condition); in tcg_qemu_tb_exec()
679 T1 = tci_uint64(regs[r3], regs[r2]); in tcg_qemu_tb_exec()
681 tci_write_reg64(regs, r1, r0, T1 + T2); in tcg_qemu_tb_exec()
687 T1 = tci_uint64(regs[r3], regs[r2]); in tcg_qemu_tb_exec()
689 tci_write_reg64(regs, r1, r0, T1 - T2); in tcg_qemu_tb_exec()
823 T1 = regs[r2] + regs[r4]; in tcg_qemu_tb_exec()
825 regs[r0] = T1; in tcg_qemu_tb_exec()
832 T1 = regs[r2] - regs[r4]; in tcg_qemu_tb_exec()
[all …]
/qemu/target/loongarch/tcg/
H A Dvec_helper.c1399 #define SSRANS(E, T1, T2) \ argument
1400 static T1 do_ssrans_ ## E(T1 e2, int sa, int sh) \
1402 T1 shft_res; \
1447 #define SSRLNU(E, T1, T2, T3) \ argument
1448 static T1 do_ssrlnu_ ## E(T3 e2, int sa, int sh) \
1450 T1 shft_res; \
1454 shft_res = (((T1)e2) >> sa); \
1493 #define SSRANU(E, T1, T2, T3) \ argument
1494 static T1 do_ssranu_ ## E(T3 e2, int sa, int sh) \
1496 T1 shft_res; \
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/qemu/target/arm/tcg/
H A Dt32.decode465 PLD 1111 1000 1001 ---- 1111 ------------ # (immediate T1)
485 PLDW 1111 1000 1011 ---- 1111 ------------ # (immediate T1)
513 PLI 1111 1001 1001 ---- 1111 ------------ # (immediate T1)
H A Dmve.decode633 # VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
699 # encodings T1, T2, T3 and the fc bits. These include VPT, which is