/qemu/include/tcg/ |
H A D | tcg-cond.h | 56 TCG_COND_LTU = 8 | 0 | 2 | 0, enumerator
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/qemu/target/arm/tcg/ |
H A D | gengvec64.c | 303 tcg_gen_movcond_i64(TCG_COND_LTU, tpos, tmp, a, max, tmp); in gen_usqadd_d() 307 tcg_gen_movcond_i64(TCG_COND_LTU, tneg, a, tneg, zero, tmp); in gen_usqadd_d()
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H A D | gengvec.c | 1014 tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero); in gen_ushl_i32() 1015 tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst); in gen_ushl_i32() 1036 tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero); in gen_ushl_i64() 1037 tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst); in gen_ushl_i64() 1323 tcg_gen_movcond_i64(TCG_COND_LTU, res, t, a, in gen_uqadd_d() 1469 tcg_gen_movcond_i64(TCG_COND_LTU, res, a, b, tcg_constant_i64(0), t); in gen_uqsub_d() 1662 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, d, t); in gen_uabd_i32() 1671 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, d, t); in gen_uabd_i64()
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_branch.c.inc | 79 TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU)
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H A D | trans_vec.c.inc | 4631 TRANS(vslt_bu, LSX, do_cmp, MO_8, TCG_COND_LTU) 4632 TRANS(vslt_hu, LSX, do_cmp, MO_16, TCG_COND_LTU) 4633 TRANS(vslt_wu, LSX, do_cmp, MO_32, TCG_COND_LTU) 4634 TRANS(vslt_du, LSX, do_cmp, MO_64, TCG_COND_LTU) 4635 TRANS(vslti_bu, LSX, do_cmpi, MO_8, TCG_COND_LTU) 4636 TRANS(vslti_hu, LSX, do_cmpi, MO_16, TCG_COND_LTU) 4637 TRANS(vslti_wu, LSX, do_cmpi, MO_32, TCG_COND_LTU) 4638 TRANS(vslti_du, LSX, do_cmpi, MO_64, TCG_COND_LTU) 4647 TRANS(xvslt_bu, LASX, do_xcmp, MO_8, TCG_COND_LTU) 4648 TRANS(xvslt_hu, LASX, do_xcmp, MO_16, TCG_COND_LTU) [all …]
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H A D | trans_arith.c.inc | 90 tcg_gen_setcond_tl(TCG_COND_LTU, dest, src1, src2);
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/qemu/tcg/sparc64/ |
H A D | tcg-target.c.inc | 619 [TCG_COND_LTU] = COND_CS, 732 case TCG_COND_LTU: 747 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); 756 cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU); 782 if (cond == TCG_COND_LTU) { 814 case TCG_COND_LTU: 878 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
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/qemu/tcg/ |
H A D | optimize.c | 627 case TCG_COND_LTU: in do_constant_folding_cond_32() 661 case TCG_COND_LTU: in do_constant_folding_cond_64() 684 case TCG_COND_LTU: in do_constant_folding_cond_eq() 729 case TCG_COND_LTU: in do_constant_folding_cond() 885 case TCG_COND_LTU: in do_constant_folding_cond2() 2129 case TCG_COND_LTU: in fold_setcond_zmask() 2155 case TCG_COND_LTU: in fold_setcond_zmask()
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H A D | tci.c | 220 case TCG_COND_LTU: in tci_compare32() 268 case TCG_COND_LTU: in tci_compare64() 1053 [TCG_COND_LTU] = "ltu", in str_c()
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H A D | tcg-op.c | 1394 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); in tcg_gen_umin_i32() 1404 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); in tcg_gen_umax_i32() 3015 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al); in tcg_gen_add2_i64() 3033 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl); in tcg_gen_sub2_i64() 3121 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); in tcg_gen_umin_i64() 3131 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); in tcg_gen_umax_i64()
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H A D | tcg-op-gvec.c | 2255 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); in tcg_gen_usadd_i32() 2262 tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); in tcg_gen_usadd_i64() 2297 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); in tcg_gen_ussub_i32() 2304 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); in tcg_gen_ussub_i64() 3749 [TCG_COND_LTU] = ltu_fn, in tcg_gen_gvec_cmp() 3871 [TCG_COND_LTU] = ltu_fn, in tcg_gen_gvec_cmps()
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvi.c.inc | 123 case TCG_COND_LTU: 134 tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl); 221 return gen_branch(ctx, a, TCG_COND_LTU); 451 tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); 457 gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
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H A D | trans_rvm.c.inc | 42 tcg_gen_setcond_tl(TCG_COND_LTU, r3, tmph, r2);
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/qemu/target/openrisc/ |
H A D | translate.c | 241 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); in gen_sub() 372 tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); in gen_macu() 412 tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); in gen_msbu() 967 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, in trans_l_sfltu() 1033 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfltui()
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/qemu/accel/tcg/ |
H A D | plugin-gen.c | 146 return TCG_COND_LTU; in plugin_cond_to_tcgcond()
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/qemu/target/ppc/translate/ |
H A D | vmx-impl.c.inc | 1378 tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt); 1383 tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt); 2282 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8), 2284 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8), 2286 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(16), 2289 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8), 2291 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8), 2293 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16), 2886 tcg_gen_cmp_vec(TCG_COND_LTU, vece, t, a, b); 2893 tcg_gen_setcond_i32(TCG_COND_LTU, t, a, b);
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/qemu/tcg/loongarch64/ |
H A D | tcg-target.c.inc | 584 cond = TCG_COND_LTU; 617 case TCG_COND_LTU: 710 [TCG_COND_LTU] = { OPC_BGTU, true }, 1820 [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU}, 1827 [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU}, 1937 } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) &&
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/qemu/target/tricore/ |
H A D | translate.c | 572 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); in gen_maddu64_d() 3045 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, in gen_compute_branch() 5188 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator() 5671 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5711 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5731 tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], in decode_rr_accumulator() 5759 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5819 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5855 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() 5908 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator() [all …]
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/qemu/target/m68k/ |
H A D | translate.c | 573 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); in gen_flush_flags() 1193 tcond = TCG_COND_LTU; in gen_cc_cond() 1830 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); in DISAS_INSN() 1833 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); in DISAS_INSN() 2276 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im); in DISAS_INSN() 2285 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im); in DISAS_INSN() 2959 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); in DISAS_INSN() 2964 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); in DISAS_INSN()
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/qemu/tcg/i386/ |
H A D | tcg-target.c.inc | 519 [TCG_COND_LTU] = JCC_JB, 1592 tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2], 1616 case TCG_COND_LTU: 1617 tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3], 1620 tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2], 1624 tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3], 1700 case TCG_COND_LTU: 1707 tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, cmp_rexw); 4031 case TCG_COND_LTU:
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/qemu/target/hexagon/idef-parser/ |
H A D | idef-parser.y | 614 $$ = gen_bin_cmp(c, &@1, TCG_COND_LTU, &$1, &$3);
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/qemu/tcg/ppc/ |
H A D | tcg-target.c.inc | 317 case TCG_COND_LTU: 730 [TCG_COND_LTU] = BC | BI(0, CR_LT) | BO_COND_TRUE, 746 [TCG_COND_LTU] = ISEL | BC_(0, CR_LT), 1835 case TCG_COND_LTU: 2054 case TCG_COND_LTU: 2182 [TCG_COND_LTU] = { CR_LT, CR_LT }, 2231 case TCG_COND_LTU: 3947 case TCG_COND_LTU:
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/qemu/target/hexagon/ |
H A D | gen_tcg.h | 1060 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV) 1062 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 423 [TCG_COND_LTU] = S390_CC_LT, 441 [TCG_COND_LTU] = S390_CC_NEVER, 577 case TCG_COND_LTU: 1323 case TCG_COND_LTU: 1371 case TCG_COND_LTU: 3058 case TCG_COND_LTU:
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/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 793 [TCG_COND_LTU] = { OPC_BLTU, false }, 855 cond = TCG_COND_LTU; 898 case TCG_COND_LTU:
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