1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "qemu/osdep.h"
19 #include "hw/hw.h"
20 #include "hw/pci/pci.h"
21 #include "hw/qdev-properties.h"
22 #include "net/tap.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu/bswap.h"
26 #include "qemu/log.h"
27 #include "qemu/module.h"
28 #include "hw/pci/msix.h"
29 #include "hw/pci/msi.h"
30 #include "migration/register.h"
31 #include "migration/vmstate.h"
32
33 #include "vmxnet3.h"
34 #include "vmxnet3_defs.h"
35 #include "vmxnet_debug.h"
36 #include "vmware_utils.h"
37 #include "net_tx_pkt.h"
38 #include "net_rx_pkt.h"
39 #include "qom/object.h"
40
41 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
42 #define VMXNET3_MSIX_BAR_SIZE 0x2000
43
44 /* Compatibility flags for migration */
45 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
46 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
47 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
48 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
49 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
50 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
51
52 #define VMXNET3_EXP_EP_OFFSET (0x48)
53 #define VMXNET3_MSI_OFFSET(s) \
54 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
55 #define VMXNET3_MSIX_OFFSET(s) \
56 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
57 #define VMXNET3_DSN_OFFSET (0x100)
58
59 #define VMXNET3_BAR0_IDX (0)
60 #define VMXNET3_BAR1_IDX (1)
61 #define VMXNET3_MSIX_BAR_IDX (2)
62
63 #define VMXNET3_OFF_MSIX_TABLE (0x000)
64 #define VMXNET3_OFF_MSIX_PBA(s) \
65 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
66
67 /* Link speed in Mbps should be shifted by 16 */
68 #define VMXNET3_LINK_SPEED (1000 << 16)
69
70 /* Link status: 1 - up, 0 - down. */
71 #define VMXNET3_LINK_STATUS_UP 0x1
72
73 /* Least significant bit should be set for revision and version */
74 #define VMXNET3_UPT_REVISION 0x1
75 #define VMXNET3_DEVICE_REVISION 0x1
76
77 /* Number of interrupt vectors for non-MSIx modes */
78 #define VMXNET3_MAX_NMSIX_INTRS (1)
79
80 /* Macros for rings descriptors access */
81 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
82 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
83
84 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
85 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
86
87 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
88 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
89
90 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
91 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
92
93 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
94 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
95
96 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
97 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
98
99 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
100 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
101
102 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
103 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
104
105 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
106 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
107
108 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
109 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
110
111 /* Macros for guest driver shared area access */
112 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
113 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
114
115 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
116 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
117
118 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
119 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
120
121 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
122 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
123
124 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
125 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
126
127 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
128 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
129
130 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
131
132 struct VMXNET3Class {
133 PCIDeviceClass parent_class;
134 DeviceRealize parent_dc_realize;
135 };
136 typedef struct VMXNET3Class VMXNET3Class;
137
DECLARE_CLASS_CHECKERS(VMXNET3Class,VMXNET3_DEVICE,TYPE_VMXNET3)138 DECLARE_CLASS_CHECKERS(VMXNET3Class, VMXNET3_DEVICE,
139 TYPE_VMXNET3)
140
141 static inline void vmxnet3_ring_init(PCIDevice *d,
142 Vmxnet3Ring *ring,
143 hwaddr pa,
144 uint32_t size,
145 uint32_t cell_size,
146 bool zero_region)
147 {
148 ring->pa = pa;
149 ring->size = size;
150 ring->cell_size = cell_size;
151 ring->gen = VMXNET3_INIT_GEN;
152 ring->next = 0;
153
154 if (zero_region) {
155 vmw_shmem_set(d, pa, 0, size * cell_size);
156 }
157 }
158
159 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
160 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
161 (ring_name), (ridx), \
162 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
163
vmxnet3_ring_inc(Vmxnet3Ring * ring)164 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
165 {
166 if (++ring->next >= ring->size) {
167 ring->next = 0;
168 ring->gen ^= 1;
169 }
170 }
171
vmxnet3_ring_dec(Vmxnet3Ring * ring)172 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
173 {
174 if (ring->next-- == 0) {
175 ring->next = ring->size - 1;
176 ring->gen ^= 1;
177 }
178 }
179
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring * ring)180 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
181 {
182 return ring->pa + ring->next * ring->cell_size;
183 }
184
vmxnet3_ring_read_curr_cell(PCIDevice * d,Vmxnet3Ring * ring,void * buff)185 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
186 void *buff)
187 {
188 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
189 }
190
vmxnet3_ring_write_curr_cell(PCIDevice * d,Vmxnet3Ring * ring,void * buff)191 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
192 void *buff)
193 {
194 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
195 }
196
vmxnet3_ring_curr_cell_idx(Vmxnet3Ring * ring)197 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
198 {
199 return ring->next;
200 }
201
vmxnet3_ring_curr_gen(Vmxnet3Ring * ring)202 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
203 {
204 return ring->gen;
205 }
206
207 /* Debug trace-related functions */
208 static inline void
vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc * descr)209 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
210 {
211 VMW_PKPRN("TX DESCR: "
212 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
213 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
214 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
215 descr->addr, descr->len, descr->gen, descr->rsvd,
216 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
217 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
218 }
219
220 static inline void
vmxnet3_dump_virt_hdr(struct virtio_net_hdr * vhdr)221 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
222 {
223 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
224 "csum_start: %d, csum_offset: %d",
225 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
226 vhdr->csum_start, vhdr->csum_offset);
227 }
228
229 static inline void
vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc * descr)230 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
231 {
232 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
233 "dtype: %d, ext1: %d, btype: %d",
234 descr->addr, descr->len, descr->gen,
235 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
236 }
237
238 /* Interrupt management */
239
240 /*
241 * This function returns sign whether interrupt line is in asserted state
242 * This depends on the type of interrupt used. For INTX interrupt line will
243 * be asserted until explicit deassertion, for MSI(X) interrupt line will
244 * be deasserted automatically due to notification semantics of the MSI(X)
245 * interrupts
246 */
_vmxnet3_assert_interrupt_line(VMXNET3State * s,uint32_t int_idx)247 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
248 {
249 PCIDevice *d = PCI_DEVICE(s);
250
251 if (s->msix_used && msix_enabled(d)) {
252 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
253 msix_notify(d, int_idx);
254 return false;
255 }
256 if (msi_enabled(d)) {
257 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
258 msi_notify(d, int_idx);
259 return false;
260 }
261
262 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
263 pci_irq_assert(d);
264 return true;
265 }
266
_vmxnet3_deassert_interrupt_line(VMXNET3State * s,int lidx)267 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
268 {
269 PCIDevice *d = PCI_DEVICE(s);
270
271 /*
272 * This function should never be called for MSI(X) interrupts
273 * because deassertion never required for message interrupts
274 */
275 assert(!s->msix_used || !msix_enabled(d));
276 /*
277 * This function should never be called for MSI(X) interrupts
278 * because deassertion never required for message interrupts
279 */
280 assert(!msi_enabled(d));
281
282 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
283 pci_irq_deassert(d);
284 }
285
vmxnet3_update_interrupt_line_state(VMXNET3State * s,int lidx)286 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
287 {
288 if (!s->interrupt_states[lidx].is_pending &&
289 s->interrupt_states[lidx].is_asserted) {
290 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
291 _vmxnet3_deassert_interrupt_line(s, lidx);
292 s->interrupt_states[lidx].is_asserted = false;
293 return;
294 }
295
296 if (s->interrupt_states[lidx].is_pending &&
297 !s->interrupt_states[lidx].is_masked &&
298 !s->interrupt_states[lidx].is_asserted) {
299 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
300 s->interrupt_states[lidx].is_asserted =
301 _vmxnet3_assert_interrupt_line(s, lidx);
302 s->interrupt_states[lidx].is_pending = false;
303 return;
304 }
305 }
306
vmxnet3_trigger_interrupt(VMXNET3State * s,int lidx)307 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
308 {
309 PCIDevice *d = PCI_DEVICE(s);
310 s->interrupt_states[lidx].is_pending = true;
311 vmxnet3_update_interrupt_line_state(s, lidx);
312
313 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
314 goto do_automask;
315 }
316
317 if (msi_enabled(d) && s->auto_int_masking) {
318 goto do_automask;
319 }
320
321 return;
322
323 do_automask:
324 s->interrupt_states[lidx].is_masked = true;
325 vmxnet3_update_interrupt_line_state(s, lidx);
326 }
327
vmxnet3_interrupt_asserted(VMXNET3State * s,int lidx)328 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
329 {
330 return s->interrupt_states[lidx].is_asserted;
331 }
332
vmxnet3_clear_interrupt(VMXNET3State * s,int int_idx)333 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
334 {
335 s->interrupt_states[int_idx].is_pending = false;
336 if (s->auto_int_masking) {
337 s->interrupt_states[int_idx].is_masked = true;
338 }
339 vmxnet3_update_interrupt_line_state(s, int_idx);
340 }
341
342 static void
vmxnet3_on_interrupt_mask_changed(VMXNET3State * s,int lidx,bool is_masked)343 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
344 {
345 s->interrupt_states[lidx].is_masked = is_masked;
346 vmxnet3_update_interrupt_line_state(s, lidx);
347 }
348
vmxnet3_verify_driver_magic(PCIDevice * d,hwaddr dshmem)349 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem)
350 {
351 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC);
352 }
353
354 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
355 #define VMXNET3_MAKE_BYTE(byte_num, val) \
356 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
357
vmxnet3_set_variable_mac(VMXNET3State * s,uint32_t h,uint32_t l)358 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
359 {
360 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
361 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
362 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
363 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
364 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
365 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
366
367 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
368
369 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
370 }
371
vmxnet3_get_mac_low(MACAddr * addr)372 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
373 {
374 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
375 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
376 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
377 VMXNET3_MAKE_BYTE(3, addr->a[3]);
378 }
379
vmxnet3_get_mac_high(MACAddr * addr)380 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
381 {
382 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
383 VMXNET3_MAKE_BYTE(1, addr->a[5]);
384 }
385
386 static void
vmxnet3_inc_tx_consumption_counter(VMXNET3State * s,int qidx)387 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
388 {
389 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
390 }
391
392 static inline void
vmxnet3_inc_rx_consumption_counter(VMXNET3State * s,int qidx,int ridx)393 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
394 {
395 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
396 }
397
398 static inline void
vmxnet3_inc_tx_completion_counter(VMXNET3State * s,int qidx)399 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
400 {
401 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
402 }
403
404 static void
vmxnet3_inc_rx_completion_counter(VMXNET3State * s,int qidx)405 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
406 {
407 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
408 }
409
410 static void
vmxnet3_dec_rx_completion_counter(VMXNET3State * s,int qidx)411 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
412 {
413 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
414 }
415
vmxnet3_complete_packet(VMXNET3State * s,int qidx,uint32_t tx_ridx)416 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)
417 {
418 struct Vmxnet3_TxCompDesc txcq_descr;
419 PCIDevice *d = PCI_DEVICE(s);
420
421 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
422
423 memset(&txcq_descr, 0, sizeof(txcq_descr));
424 txcq_descr.txdIdx = tx_ridx;
425 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
426 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1);
427 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2);
428 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);
429
430 /* Flush changes in TX descriptor before changing the counter value */
431 smp_wmb();
432
433 vmxnet3_inc_tx_completion_counter(s, qidx);
434 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
435 }
436
437 static bool
vmxnet3_setup_tx_offloads(VMXNET3State * s)438 vmxnet3_setup_tx_offloads(VMXNET3State *s)
439 {
440 switch (s->offload_mode) {
441 case VMXNET3_OM_NONE:
442 return net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
443
444 case VMXNET3_OM_CSUM:
445 VMW_PKPRN("L4 CSO requested\n");
446 return net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
447
448 case VMXNET3_OM_TSO:
449 VMW_PKPRN("GSO offload requested.");
450 if (!net_tx_pkt_build_vheader(s->tx_pkt, true, true,
451 s->cso_or_gso_size)) {
452 return false;
453 }
454 net_tx_pkt_update_ip_checksums(s->tx_pkt);
455 break;
456
457 default:
458 g_assert_not_reached();
459 }
460
461 return true;
462 }
463
464 static void
vmxnet3_tx_retrieve_metadata(VMXNET3State * s,const struct Vmxnet3_TxDesc * txd)465 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
466 const struct Vmxnet3_TxDesc *txd)
467 {
468 s->offload_mode = txd->om;
469 s->cso_or_gso_size = txd->msscof;
470 s->tci = txd->tci;
471 s->needs_vlan = txd->ti;
472 }
473
474 typedef enum {
475 VMXNET3_PKT_STATUS_OK,
476 VMXNET3_PKT_STATUS_ERROR,
477 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
478 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
479 } Vmxnet3PktStatus;
480
481 static void
vmxnet3_on_tx_done_update_stats(VMXNET3State * s,int qidx,Vmxnet3PktStatus status)482 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
483 Vmxnet3PktStatus status)
484 {
485 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt);
486 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
487
488 switch (status) {
489 case VMXNET3_PKT_STATUS_OK:
490 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) {
491 case ETH_PKT_BCAST:
492 stats->bcastPktsTxOK++;
493 stats->bcastBytesTxOK += tot_len;
494 break;
495 case ETH_PKT_MCAST:
496 stats->mcastPktsTxOK++;
497 stats->mcastBytesTxOK += tot_len;
498 break;
499 case ETH_PKT_UCAST:
500 stats->ucastPktsTxOK++;
501 stats->ucastBytesTxOK += tot_len;
502 break;
503 default:
504 g_assert_not_reached();
505 }
506
507 if (s->offload_mode == VMXNET3_OM_TSO) {
508 /*
509 * According to VMWARE headers this statistic is a number
510 * of packets after segmentation but since we don't have
511 * this information in QEMU model, the best we can do is to
512 * provide number of non-segmented packets
513 */
514 stats->TSOPktsTxOK++;
515 stats->TSOBytesTxOK += tot_len;
516 }
517 break;
518
519 case VMXNET3_PKT_STATUS_DISCARD:
520 stats->pktsTxDiscard++;
521 break;
522
523 case VMXNET3_PKT_STATUS_ERROR:
524 stats->pktsTxError++;
525 break;
526
527 default:
528 g_assert_not_reached();
529 }
530 }
531
532 static void
vmxnet3_on_rx_done_update_stats(VMXNET3State * s,int qidx,Vmxnet3PktStatus status)533 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
534 int qidx,
535 Vmxnet3PktStatus status)
536 {
537 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
538 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt);
539
540 switch (status) {
541 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
542 stats->pktsRxOutOfBuf++;
543 break;
544
545 case VMXNET3_PKT_STATUS_ERROR:
546 stats->pktsRxError++;
547 break;
548 case VMXNET3_PKT_STATUS_OK:
549 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
550 case ETH_PKT_BCAST:
551 stats->bcastPktsRxOK++;
552 stats->bcastBytesRxOK += tot_len;
553 break;
554 case ETH_PKT_MCAST:
555 stats->mcastPktsRxOK++;
556 stats->mcastBytesRxOK += tot_len;
557 break;
558 case ETH_PKT_UCAST:
559 stats->ucastPktsRxOK++;
560 stats->ucastBytesRxOK += tot_len;
561 break;
562 default:
563 g_assert_not_reached();
564 }
565
566 if (tot_len > s->mtu) {
567 stats->LROPktsRxOK++;
568 stats->LROBytesRxOK += tot_len;
569 }
570 break;
571 default:
572 g_assert_not_reached();
573 }
574 }
575
576 static inline void
vmxnet3_ring_read_curr_txdesc(PCIDevice * pcidev,Vmxnet3Ring * ring,struct Vmxnet3_TxDesc * txd)577 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring,
578 struct Vmxnet3_TxDesc *txd)
579 {
580 vmxnet3_ring_read_curr_cell(pcidev, ring, txd);
581 txd->addr = le64_to_cpu(txd->addr);
582 txd->val1 = le32_to_cpu(txd->val1);
583 txd->val2 = le32_to_cpu(txd->val2);
584 }
585
586 static inline bool
vmxnet3_pop_next_tx_descr(VMXNET3State * s,int qidx,struct Vmxnet3_TxDesc * txd,uint32_t * descr_idx)587 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
588 int qidx,
589 struct Vmxnet3_TxDesc *txd,
590 uint32_t *descr_idx)
591 {
592 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
593 PCIDevice *d = PCI_DEVICE(s);
594
595 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
596 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
597 /* Only read after generation field verification */
598 smp_rmb();
599 /* Re-read to be sure we got the latest version */
600 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
601 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
602 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
603 vmxnet3_inc_tx_consumption_counter(s, qidx);
604 return true;
605 }
606
607 return false;
608 }
609
610 static bool
vmxnet3_send_packet(VMXNET3State * s,uint32_t qidx)611 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
612 {
613 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
614
615 if (!vmxnet3_setup_tx_offloads(s)) {
616 status = VMXNET3_PKT_STATUS_ERROR;
617 goto func_exit;
618 }
619
620 /* debug prints */
621 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt));
622 net_tx_pkt_dump(s->tx_pkt);
623
624 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
625 status = VMXNET3_PKT_STATUS_DISCARD;
626 goto func_exit;
627 }
628
629 func_exit:
630 vmxnet3_on_tx_done_update_stats(s, qidx, status);
631 return (status == VMXNET3_PKT_STATUS_OK);
632 }
633
vmxnet3_process_tx_queue(VMXNET3State * s,int qidx)634 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
635 {
636 struct Vmxnet3_TxDesc txd;
637 uint32_t txd_idx;
638 uint32_t data_len;
639 hwaddr data_pa;
640
641 for (;;) {
642 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
643 break;
644 }
645
646 vmxnet3_dump_tx_descr(&txd);
647
648 if (!s->skip_current_tx_pkt) {
649 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
650 data_pa = txd.addr;
651
652 if (!net_tx_pkt_add_raw_fragment_pci(s->tx_pkt, PCI_DEVICE(s),
653 data_pa, data_len)) {
654 s->skip_current_tx_pkt = true;
655 }
656 }
657
658 if (s->tx_sop) {
659 vmxnet3_tx_retrieve_metadata(s, &txd);
660 s->tx_sop = false;
661 }
662
663 if (txd.eop) {
664 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) {
665 if (s->needs_vlan) {
666 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
667 }
668
669 vmxnet3_send_packet(s, qidx);
670 } else {
671 vmxnet3_on_tx_done_update_stats(s, qidx,
672 VMXNET3_PKT_STATUS_ERROR);
673 }
674
675 vmxnet3_complete_packet(s, qidx, txd_idx);
676 s->tx_sop = true;
677 s->skip_current_tx_pkt = false;
678 net_tx_pkt_reset(s->tx_pkt,
679 net_tx_pkt_unmap_frag_pci, PCI_DEVICE(s));
680 }
681 }
682
683 net_tx_pkt_reset(s->tx_pkt, net_tx_pkt_unmap_frag_pci, PCI_DEVICE(s));
684 }
685
686 static inline void
vmxnet3_read_next_rx_descr(VMXNET3State * s,int qidx,int ridx,struct Vmxnet3_RxDesc * dbuf,uint32_t * didx)687 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
688 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
689 {
690 PCIDevice *d = PCI_DEVICE(s);
691
692 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
693 *didx = vmxnet3_ring_curr_cell_idx(ring);
694 vmxnet3_ring_read_curr_cell(d, ring, dbuf);
695 dbuf->addr = le64_to_cpu(dbuf->addr);
696 dbuf->val1 = le32_to_cpu(dbuf->val1);
697 dbuf->ext1 = le32_to_cpu(dbuf->ext1);
698 }
699
700 static inline uint8_t
vmxnet3_get_rx_ring_gen(VMXNET3State * s,int qidx,int ridx)701 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
702 {
703 return s->rxq_descr[qidx].rx_ring[ridx].gen;
704 }
705
706 static inline hwaddr
vmxnet3_pop_rxc_descr(VMXNET3State * s,int qidx,uint32_t * descr_gen)707 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
708 {
709 uint8_t ring_gen;
710 struct Vmxnet3_RxCompDesc rxcd;
711
712 hwaddr daddr =
713 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
714
715 pci_dma_read(PCI_DEVICE(s),
716 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
717 rxcd.val1 = le32_to_cpu(rxcd.val1);
718 rxcd.val2 = le32_to_cpu(rxcd.val2);
719 rxcd.val3 = le32_to_cpu(rxcd.val3);
720 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
721
722 if (rxcd.gen != ring_gen) {
723 *descr_gen = ring_gen;
724 vmxnet3_inc_rx_completion_counter(s, qidx);
725 return daddr;
726 }
727
728 return 0;
729 }
730
731 static inline void
vmxnet3_revert_rxc_descr(VMXNET3State * s,int qidx)732 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
733 {
734 vmxnet3_dec_rx_completion_counter(s, qidx);
735 }
736
737 #define RXQ_IDX (0)
738 #define RX_HEAD_BODY_RING (0)
739 #define RX_BODY_ONLY_RING (1)
740
741 static bool
vmxnet3_get_next_head_rx_descr(VMXNET3State * s,struct Vmxnet3_RxDesc * descr_buf,uint32_t * descr_idx,uint32_t * ridx)742 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
743 struct Vmxnet3_RxDesc *descr_buf,
744 uint32_t *descr_idx,
745 uint32_t *ridx)
746 {
747 for (;;) {
748 uint32_t ring_gen;
749 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
750 descr_buf, descr_idx);
751
752 /* If no more free descriptors - return */
753 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
754 if (descr_buf->gen != ring_gen) {
755 return false;
756 }
757
758 /* Only read after generation field verification */
759 smp_rmb();
760 /* Re-read to be sure we got the latest version */
761 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
762 descr_buf, descr_idx);
763
764 /* Mark current descriptor as used/skipped */
765 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
766
767 /* If this is what we are looking for - return */
768 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
769 *ridx = RX_HEAD_BODY_RING;
770 return true;
771 }
772 }
773 }
774
775 static bool
vmxnet3_get_next_body_rx_descr(VMXNET3State * s,struct Vmxnet3_RxDesc * d,uint32_t * didx,uint32_t * ridx)776 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
777 struct Vmxnet3_RxDesc *d,
778 uint32_t *didx,
779 uint32_t *ridx)
780 {
781 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
782
783 /* Try to find corresponding descriptor in head/body ring */
784 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
785 /* Only read after generation field verification */
786 smp_rmb();
787 /* Re-read to be sure we got the latest version */
788 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
789 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
790 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
791 *ridx = RX_HEAD_BODY_RING;
792 return true;
793 }
794 }
795
796 /*
797 * If there is no free descriptors on head/body ring or next free
798 * descriptor is a head descriptor switch to body only ring
799 */
800 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
801
802 /* If no more free descriptors - return */
803 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
804 /* Only read after generation field verification */
805 smp_rmb();
806 /* Re-read to be sure we got the latest version */
807 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
808 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
809 *ridx = RX_BODY_ONLY_RING;
810 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
811 return true;
812 }
813
814 return false;
815 }
816
817 static inline bool
vmxnet3_get_next_rx_descr(VMXNET3State * s,bool is_head,struct Vmxnet3_RxDesc * descr_buf,uint32_t * descr_idx,uint32_t * ridx)818 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
819 struct Vmxnet3_RxDesc *descr_buf,
820 uint32_t *descr_idx,
821 uint32_t *ridx)
822 {
823 if (is_head || !s->rx_packets_compound) {
824 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
825 } else {
826 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
827 }
828 }
829
830 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
831 * the implementation always passes an RxCompDesc with a "Checksum
832 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
833 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
834 *
835 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
836 * and place a fully computed checksum into the tcp/udp header.
837 * Otherwise, the OS driver will receive a checksum-correct indication
838 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
839 * having just the pseudo header csum value.
840 *
841 * While this is not a problem if packet is destined for local delivery,
842 * in the case the host OS performs forwarding, it will forward an
843 * incorrectly checksummed packet.
844 */
vmxnet3_rx_need_csum_calculate(struct NetRxPkt * pkt,const void * pkt_data,size_t pkt_len)845 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt,
846 const void *pkt_data,
847 size_t pkt_len)
848 {
849 struct virtio_net_hdr *vhdr;
850 bool hasip4, hasip6;
851 EthL4HdrProto l4hdr_proto;
852 uint8_t *data;
853 int len;
854
855 vhdr = net_rx_pkt_get_vhdr(pkt);
856 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
857 return;
858 }
859
860 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
861 if (!(hasip4 || hasip6) ||
862 (l4hdr_proto != ETH_L4_HDR_PROTO_TCP &&
863 l4hdr_proto != ETH_L4_HDR_PROTO_UDP)) {
864 return;
865 }
866
867 vmxnet3_dump_virt_hdr(vhdr);
868
869 /* Validate packet len: csum_start + scum_offset + length of csum field */
870 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
871 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
872 "cannot calculate checksum",
873 pkt_len, vhdr->csum_start, vhdr->csum_offset);
874 return;
875 }
876
877 data = (uint8_t *)pkt_data + vhdr->csum_start;
878 len = pkt_len - vhdr->csum_start;
879 /* Put the checksum obtained into the packet */
880 stw_be_p(data + vhdr->csum_offset,
881 net_checksum_finish_nozero(net_checksum_add(len, data)));
882
883 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
884 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
885 }
886
vmxnet3_rx_update_descr(struct NetRxPkt * pkt,struct Vmxnet3_RxCompDesc * rxcd)887 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt,
888 struct Vmxnet3_RxCompDesc *rxcd)
889 {
890 int csum_ok, is_gso;
891 bool hasip4, hasip6;
892 EthL4HdrProto l4hdr_proto;
893 struct virtio_net_hdr *vhdr;
894 uint8_t offload_type;
895
896 if (net_rx_pkt_is_vlan_stripped(pkt)) {
897 rxcd->ts = 1;
898 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt);
899 }
900
901 vhdr = net_rx_pkt_get_vhdr(pkt);
902 /*
903 * Checksum is valid when lower level tell so or when lower level
904 * requires checksum offload telling that packet produced/bridged
905 * locally and did travel over network after last checksum calculation
906 * or production
907 */
908 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
909 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
910
911 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
912 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
913
914 if (!csum_ok && !is_gso) {
915 goto nocsum;
916 }
917
918 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
919 if ((l4hdr_proto != ETH_L4_HDR_PROTO_TCP &&
920 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) ||
921 (!hasip4 && !hasip6)) {
922 goto nocsum;
923 }
924
925 rxcd->cnc = 0;
926 rxcd->v4 = hasip4 ? 1 : 0;
927 rxcd->v6 = hasip6 ? 1 : 0;
928 rxcd->tcp = l4hdr_proto == ETH_L4_HDR_PROTO_TCP;
929 rxcd->udp = l4hdr_proto == ETH_L4_HDR_PROTO_UDP;
930 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
931 return;
932
933 nocsum:
934 rxcd->cnc = 1;
935 return;
936 }
937
938 static void
vmxnet3_pci_dma_writev(PCIDevice * pci_dev,const struct iovec * iov,size_t start_iov_off,hwaddr target_addr,size_t bytes_to_copy)939 vmxnet3_pci_dma_writev(PCIDevice *pci_dev,
940 const struct iovec *iov,
941 size_t start_iov_off,
942 hwaddr target_addr,
943 size_t bytes_to_copy)
944 {
945 size_t curr_off = 0;
946 size_t copied = 0;
947
948 while (bytes_to_copy) {
949 if (start_iov_off < (curr_off + iov->iov_len)) {
950 size_t chunk_len =
951 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
952
953 pci_dma_write(pci_dev, target_addr + copied,
954 iov->iov_base + start_iov_off - curr_off,
955 chunk_len);
956
957 copied += chunk_len;
958 start_iov_off += chunk_len;
959 curr_off = start_iov_off;
960 bytes_to_copy -= chunk_len;
961 } else {
962 curr_off += iov->iov_len;
963 }
964 iov++;
965 }
966 }
967
968 static void
vmxnet3_pci_dma_write_rxcd(PCIDevice * pcidev,dma_addr_t pa,struct Vmxnet3_RxCompDesc * rxcd)969 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa,
970 struct Vmxnet3_RxCompDesc *rxcd)
971 {
972 rxcd->val1 = cpu_to_le32(rxcd->val1);
973 rxcd->val2 = cpu_to_le32(rxcd->val2);
974 rxcd->val3 = cpu_to_le32(rxcd->val3);
975 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd));
976 }
977
978 static bool
vmxnet3_indicate_packet(VMXNET3State * s)979 vmxnet3_indicate_packet(VMXNET3State *s)
980 {
981 struct Vmxnet3_RxDesc rxd;
982 PCIDevice *d = PCI_DEVICE(s);
983 bool is_head = true;
984 uint32_t rxd_idx;
985 uint32_t rx_ridx = 0;
986
987 struct Vmxnet3_RxCompDesc rxcd;
988 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
989 hwaddr new_rxcd_pa = 0;
990 hwaddr ready_rxcd_pa = 0;
991 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt);
992 size_t bytes_copied = 0;
993 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt);
994 uint16_t num_frags = 0;
995 size_t chunk_size;
996
997 net_rx_pkt_dump(s->rx_pkt);
998
999 while (bytes_left > 0) {
1000
1001 /* cannot add more frags to packet */
1002 if (num_frags == s->max_rx_frags) {
1003 break;
1004 }
1005
1006 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1007 if (!new_rxcd_pa) {
1008 break;
1009 }
1010
1011 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1012 break;
1013 }
1014
1015 chunk_size = MIN(bytes_left, rxd.len);
1016 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size);
1017 bytes_copied += chunk_size;
1018 bytes_left -= chunk_size;
1019
1020 vmxnet3_dump_rx_descr(&rxd);
1021
1022 if (ready_rxcd_pa != 0) {
1023 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
1024 }
1025
1026 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1027 rxcd.rxdIdx = rxd_idx;
1028 rxcd.len = chunk_size;
1029 rxcd.sop = is_head;
1030 rxcd.gen = new_rxcd_gen;
1031 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1032
1033 if (bytes_left == 0) {
1034 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1035 }
1036
1037 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1038 "sop %d csum_correct %lu",
1039 (unsigned long) rx_ridx,
1040 (unsigned long) rxcd.rxdIdx,
1041 (unsigned long) rxcd.len,
1042 (int) rxcd.sop,
1043 (unsigned long) rxcd.tuc);
1044
1045 is_head = false;
1046 ready_rxcd_pa = new_rxcd_pa;
1047 new_rxcd_pa = 0;
1048 num_frags++;
1049 }
1050
1051 if (ready_rxcd_pa != 0) {
1052 rxcd.eop = 1;
1053 rxcd.err = (bytes_left != 0);
1054
1055 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
1056
1057 /* Flush RX descriptor changes */
1058 smp_wmb();
1059 }
1060
1061 if (new_rxcd_pa != 0) {
1062 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1063 }
1064
1065 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1066
1067 if (bytes_left == 0) {
1068 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1069 return true;
1070 } else if (num_frags == s->max_rx_frags) {
1071 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1072 return false;
1073 } else {
1074 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1075 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1076 return false;
1077 }
1078 }
1079
1080 static void
vmxnet3_io_bar0_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)1081 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1082 uint64_t val, unsigned size)
1083 {
1084 VMXNET3State *s = opaque;
1085
1086 if (!s->device_active) {
1087 return;
1088 }
1089
1090 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1091 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1092 int tx_queue_idx =
1093 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1094 VMXNET3_REG_ALIGN);
1095 if (tx_queue_idx <= s->txq_num) {
1096 vmxnet3_process_tx_queue(s, tx_queue_idx);
1097 } else {
1098 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Illegal TX queue %d/%d\n",
1099 tx_queue_idx, s->txq_num);
1100 }
1101 return;
1102 }
1103
1104 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1105 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1106 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1107 VMXNET3_REG_ALIGN);
1108
1109 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1110
1111 vmxnet3_on_interrupt_mask_changed(s, l, val);
1112 return;
1113 }
1114
1115 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1116 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1117 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1118 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1119 return;
1120 }
1121
1122 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1123 (uint64_t) addr, val, size);
1124 }
1125
1126 static uint64_t
vmxnet3_io_bar0_read(void * opaque,hwaddr addr,unsigned size)1127 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1128 {
1129 VMXNET3State *s = opaque;
1130
1131 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1132 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1133 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1134 VMXNET3_REG_ALIGN);
1135 return s->interrupt_states[l].is_masked;
1136 }
1137
1138 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1139 return 0;
1140 }
1141
vmxnet3_reset_interrupt_states(VMXNET3State * s)1142 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1143 {
1144 int i;
1145 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1146 s->interrupt_states[i].is_asserted = false;
1147 s->interrupt_states[i].is_pending = false;
1148 s->interrupt_states[i].is_masked = true;
1149 }
1150 }
1151
vmxnet3_reset_mac(VMXNET3State * s)1152 static void vmxnet3_reset_mac(VMXNET3State *s)
1153 {
1154 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1155 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
1156 }
1157
vmxnet3_deactivate_device(VMXNET3State * s)1158 static void vmxnet3_deactivate_device(VMXNET3State *s)
1159 {
1160 if (s->device_active) {
1161 VMW_CBPRN("Deactivating vmxnet3...");
1162 net_tx_pkt_uninit(s->tx_pkt);
1163 net_rx_pkt_uninit(s->rx_pkt);
1164 s->device_active = false;
1165 }
1166 }
1167
vmxnet3_reset(VMXNET3State * s)1168 static void vmxnet3_reset(VMXNET3State *s)
1169 {
1170 VMW_CBPRN("Resetting vmxnet3...");
1171
1172 vmxnet3_deactivate_device(s);
1173 vmxnet3_reset_interrupt_states(s);
1174 s->drv_shmem = 0;
1175 s->tx_sop = true;
1176 s->skip_current_tx_pkt = false;
1177 }
1178
vmxnet3_update_rx_mode(VMXNET3State * s)1179 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1180 {
1181 PCIDevice *d = PCI_DEVICE(s);
1182
1183 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
1184 devRead.rxFilterConf.rxMode);
1185 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1186 }
1187
vmxnet3_update_vlan_filters(VMXNET3State * s)1188 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1189 {
1190 int i;
1191 PCIDevice *d = PCI_DEVICE(s);
1192
1193 /* Copy configuration from shared memory */
1194 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem,
1195 devRead.rxFilterConf.vfTable,
1196 s->vlan_table,
1197 sizeof(s->vlan_table));
1198
1199 /* Invert byte order when needed */
1200 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1201 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1202 }
1203
1204 /* Dump configuration for debugging purposes */
1205 VMW_CFPRN("Configured VLANs:");
1206 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1207 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1208 VMW_CFPRN("\tVLAN %d is present", i);
1209 }
1210 }
1211 }
1212
vmxnet3_update_mcast_filters(VMXNET3State * s)1213 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1214 {
1215 PCIDevice *d = PCI_DEVICE(s);
1216
1217 uint16_t list_bytes =
1218 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem,
1219 devRead.rxFilterConf.mfTableLen);
1220
1221 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1222
1223 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1224 if (!s->mcast_list) {
1225 if (s->mcast_list_len == 0) {
1226 VMW_CFPRN("Current multicast list is empty");
1227 } else {
1228 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1229 s->mcast_list_len);
1230 }
1231 s->mcast_list_len = 0;
1232 } else {
1233 int i;
1234 hwaddr mcast_list_pa =
1235 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem,
1236 devRead.rxFilterConf.mfTablePA);
1237
1238 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes);
1239
1240 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1241 for (i = 0; i < s->mcast_list_len; i++) {
1242 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a));
1243 }
1244 }
1245 }
1246
vmxnet3_setup_rx_filtering(VMXNET3State * s)1247 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1248 {
1249 vmxnet3_update_rx_mode(s);
1250 vmxnet3_update_vlan_filters(s);
1251 vmxnet3_update_mcast_filters(s);
1252 }
1253
vmxnet3_get_interrupt_config(VMXNET3State * s)1254 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1255 {
1256 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1257 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1258 return interrupt_mode;
1259 }
1260
vmxnet3_fill_stats(VMXNET3State * s)1261 static void vmxnet3_fill_stats(VMXNET3State *s)
1262 {
1263 int i;
1264 PCIDevice *d = PCI_DEVICE(s);
1265
1266 if (!s->device_active)
1267 return;
1268
1269 for (i = 0; i < s->txq_num; i++) {
1270 pci_dma_write(d,
1271 s->txq_descr[i].tx_stats_pa,
1272 &s->txq_descr[i].txq_stats,
1273 sizeof(s->txq_descr[i].txq_stats));
1274 }
1275
1276 for (i = 0; i < s->rxq_num; i++) {
1277 pci_dma_write(d,
1278 s->rxq_descr[i].rx_stats_pa,
1279 &s->rxq_descr[i].rxq_stats,
1280 sizeof(s->rxq_descr[i].rxq_stats));
1281 }
1282 }
1283
vmxnet3_adjust_by_guest_type(VMXNET3State * s)1284 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1285 {
1286 struct Vmxnet3_GOSInfo gos;
1287 PCIDevice *d = PCI_DEVICE(s);
1288
1289 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos,
1290 &gos, sizeof(gos));
1291 s->rx_packets_compound =
1292 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1293
1294 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1295 }
1296
1297 static void
vmxnet3_dump_conf_descr(const char * name,struct Vmxnet3_VariableLenConfDesc * pm_descr)1298 vmxnet3_dump_conf_descr(const char *name,
1299 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1300 {
1301 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1302 name, pm_descr->confVer, pm_descr->confLen);
1303
1304 };
1305
vmxnet3_update_pm_state(VMXNET3State * s)1306 static void vmxnet3_update_pm_state(VMXNET3State *s)
1307 {
1308 struct Vmxnet3_VariableLenConfDesc pm_descr;
1309 PCIDevice *d = PCI_DEVICE(s);
1310
1311 pm_descr.confLen =
1312 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen);
1313 pm_descr.confVer =
1314 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer);
1315 pm_descr.confPA =
1316 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA);
1317
1318 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1319 }
1320
vmxnet3_update_features(VMXNET3State * s)1321 static void vmxnet3_update_features(VMXNET3State *s)
1322 {
1323 uint32_t guest_features;
1324 int rxcso_supported;
1325 PCIDevice *d = PCI_DEVICE(s);
1326
1327 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
1328 devRead.misc.uptFeatures);
1329
1330 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1331 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1332 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1333
1334 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1335 s->lro_supported, rxcso_supported,
1336 s->rx_vlan_stripping);
1337 if (s->peer_has_vhdr) {
1338 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1339 rxcso_supported,
1340 s->lro_supported,
1341 s->lro_supported,
1342 0,
1343 0,
1344 0,
1345 0);
1346 }
1347 }
1348
vmxnet3_verify_intx(VMXNET3State * s,int intx)1349 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1350 {
1351 return s->msix_used || msi_enabled(PCI_DEVICE(s))
1352 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1;
1353 }
1354
vmxnet3_validate_interrupt_idx(bool is_msix,int idx)1355 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1356 {
1357 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1358 if (idx >= max_ints) {
1359 hw_error("Bad interrupt index: %d\n", idx);
1360 }
1361 }
1362
vmxnet3_validate_interrupts(VMXNET3State * s)1363 static void vmxnet3_validate_interrupts(VMXNET3State *s)
1364 {
1365 int i;
1366
1367 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1368 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1369
1370 for (i = 0; i < s->txq_num; i++) {
1371 int idx = s->txq_descr[i].intr_idx;
1372 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1373 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1374 }
1375
1376 for (i = 0; i < s->rxq_num; i++) {
1377 int idx = s->rxq_descr[i].intr_idx;
1378 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1379 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1380 }
1381 }
1382
vmxnet3_validate_queues(VMXNET3State * s)1383 static bool vmxnet3_validate_queues(VMXNET3State *s)
1384 {
1385 /*
1386 * txq_num and rxq_num are total number of queues
1387 * configured by guest. These numbers must not
1388 * exceed corresponding maximal values.
1389 */
1390
1391 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1392 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad TX queues number: %d\n",
1393 s->txq_num);
1394 return false;
1395 }
1396
1397 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1398 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad RX queues number: %d\n",
1399 s->rxq_num);
1400 return false;
1401 }
1402
1403 return true;
1404 }
1405
vmxnet3_activate_device(VMXNET3State * s)1406 static void vmxnet3_activate_device(VMXNET3State *s)
1407 {
1408 int i;
1409 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1410 PCIDevice *d = PCI_DEVICE(s);
1411 hwaddr qdescr_table_pa;
1412 uint64_t pa;
1413 uint32_t size;
1414
1415 /* Verify configuration consistency */
1416 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) {
1417 VMW_ERPRN("Device configuration received from driver is invalid");
1418 return;
1419 }
1420
1421 /* Verify if device is active */
1422 if (s->device_active) {
1423 VMW_CFPRN("Vmxnet3 device is active");
1424 return;
1425 }
1426
1427 s->txq_num =
1428 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues);
1429 s->rxq_num =
1430 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues);
1431
1432 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1433 if (!vmxnet3_validate_queues(s)) {
1434 return;
1435 }
1436
1437 vmxnet3_adjust_by_guest_type(s);
1438 vmxnet3_update_features(s);
1439 vmxnet3_update_pm_state(s);
1440 vmxnet3_setup_rx_filtering(s);
1441 /* Cache fields from shared memory */
1442 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu);
1443 if (s->mtu < VMXNET3_MIN_MTU || s->mtu > VMXNET3_MAX_MTU) {
1444 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad MTU size: %u\n", s->mtu);
1445 return;
1446 }
1447 VMW_CFPRN("MTU is %u", s->mtu);
1448
1449 s->max_rx_frags =
1450 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG);
1451
1452 if (s->max_rx_frags == 0) {
1453 s->max_rx_frags = 1;
1454 }
1455
1456 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1457
1458 s->event_int_idx =
1459 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx);
1460 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1461 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1462
1463 s->auto_int_masking =
1464 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask);
1465 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1466
1467 qdescr_table_pa =
1468 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA);
1469 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1470
1471 /*
1472 * Worst-case scenario is a packet that holds all TX rings space so
1473 * we calculate total size of all TX rings for max TX fragments number
1474 */
1475 s->max_tx_frags = 0;
1476
1477 /* TX queues */
1478 for (i = 0; i < s->txq_num; i++) {
1479 hwaddr qdescr_pa =
1480 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1481
1482 /* Read interrupt number for this TX queue */
1483 s->txq_descr[i].intr_idx =
1484 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx);
1485 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1486
1487 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1488
1489 /* Read rings memory locations for TX queues */
1490 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA);
1491 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize);
1492 if (size > VMXNET3_TX_RING_MAX_SIZE) {
1493 size = VMXNET3_TX_RING_MAX_SIZE;
1494 }
1495
1496 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size,
1497 sizeof(struct Vmxnet3_TxDesc), false);
1498 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1499
1500 s->max_tx_frags += size;
1501
1502 /* TXC ring */
1503 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA);
1504 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize);
1505 if (size > VMXNET3_TC_RING_MAX_SIZE) {
1506 size = VMXNET3_TC_RING_MAX_SIZE;
1507 }
1508 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size,
1509 sizeof(struct Vmxnet3_TxCompDesc), true);
1510 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1511
1512 s->txq_descr[i].tx_stats_pa =
1513 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1514
1515 memset(&s->txq_descr[i].txq_stats, 0,
1516 sizeof(s->txq_descr[i].txq_stats));
1517
1518 /* Fill device-managed parameters for queues */
1519 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
1520 ctrl.txThreshold,
1521 VMXNET3_DEF_TX_THRESHOLD);
1522 }
1523
1524 /* Preallocate TX packet wrapper */
1525 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1526 net_tx_pkt_init(&s->tx_pkt, s->max_tx_frags);
1527 net_rx_pkt_init(&s->rx_pkt);
1528
1529 /* Read rings memory locations for RX queues */
1530 for (i = 0; i < s->rxq_num; i++) {
1531 int j;
1532 hwaddr qd_pa =
1533 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1534 i * sizeof(struct Vmxnet3_RxQueueDesc);
1535
1536 /* Read interrupt number for this RX queue */
1537 s->rxq_descr[i].intr_idx =
1538 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx);
1539 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1540
1541 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1542
1543 /* Read rings memory locations */
1544 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1545 /* RX rings */
1546 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]);
1547 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]);
1548 if (size > VMXNET3_RX_RING_MAX_SIZE) {
1549 size = VMXNET3_RX_RING_MAX_SIZE;
1550 }
1551 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size,
1552 sizeof(struct Vmxnet3_RxDesc), false);
1553 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1554 i, j, pa, size);
1555 }
1556
1557 /* RXC ring */
1558 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA);
1559 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize);
1560 if (size > VMXNET3_RC_RING_MAX_SIZE) {
1561 size = VMXNET3_RC_RING_MAX_SIZE;
1562 }
1563 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size,
1564 sizeof(struct Vmxnet3_RxCompDesc), true);
1565 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1566
1567 s->rxq_descr[i].rx_stats_pa =
1568 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1569 memset(&s->rxq_descr[i].rxq_stats, 0,
1570 sizeof(s->rxq_descr[i].rxq_stats));
1571 }
1572
1573 vmxnet3_validate_interrupts(s);
1574
1575 /* Make sure everything is in place before device activation */
1576 smp_wmb();
1577
1578 vmxnet3_reset_mac(s);
1579
1580 s->device_active = true;
1581 }
1582
vmxnet3_handle_command(VMXNET3State * s,uint64_t cmd)1583 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1584 {
1585 s->last_command = cmd;
1586
1587 switch (cmd) {
1588 case VMXNET3_CMD_GET_PERM_MAC_HI:
1589 VMW_CBPRN("Set: Get upper part of permanent MAC");
1590 break;
1591
1592 case VMXNET3_CMD_GET_PERM_MAC_LO:
1593 VMW_CBPRN("Set: Get lower part of permanent MAC");
1594 break;
1595
1596 case VMXNET3_CMD_GET_STATS:
1597 VMW_CBPRN("Set: Get device statistics");
1598 vmxnet3_fill_stats(s);
1599 break;
1600
1601 case VMXNET3_CMD_ACTIVATE_DEV:
1602 VMW_CBPRN("Set: Activating vmxnet3 device");
1603 vmxnet3_activate_device(s);
1604 break;
1605
1606 case VMXNET3_CMD_UPDATE_RX_MODE:
1607 VMW_CBPRN("Set: Update rx mode");
1608 vmxnet3_update_rx_mode(s);
1609 break;
1610
1611 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1612 VMW_CBPRN("Set: Update VLAN filters");
1613 vmxnet3_update_vlan_filters(s);
1614 break;
1615
1616 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1617 VMW_CBPRN("Set: Update MAC filters");
1618 vmxnet3_update_mcast_filters(s);
1619 break;
1620
1621 case VMXNET3_CMD_UPDATE_FEATURE:
1622 VMW_CBPRN("Set: Update features");
1623 vmxnet3_update_features(s);
1624 break;
1625
1626 case VMXNET3_CMD_UPDATE_PMCFG:
1627 VMW_CBPRN("Set: Update power management config");
1628 vmxnet3_update_pm_state(s);
1629 break;
1630
1631 case VMXNET3_CMD_GET_LINK:
1632 VMW_CBPRN("Set: Get link");
1633 break;
1634
1635 case VMXNET3_CMD_RESET_DEV:
1636 VMW_CBPRN("Set: Reset device");
1637 vmxnet3_reset(s);
1638 break;
1639
1640 case VMXNET3_CMD_QUIESCE_DEV:
1641 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1642 vmxnet3_deactivate_device(s);
1643 break;
1644
1645 case VMXNET3_CMD_GET_CONF_INTR:
1646 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1647 break;
1648
1649 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1650 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1651 "adaptive ring info flags");
1652 break;
1653
1654 case VMXNET3_CMD_GET_DID_LO:
1655 VMW_CBPRN("Set: Get lower part of device ID");
1656 break;
1657
1658 case VMXNET3_CMD_GET_DID_HI:
1659 VMW_CBPRN("Set: Get upper part of device ID");
1660 break;
1661
1662 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1663 VMW_CBPRN("Set: Get device extra info");
1664 break;
1665
1666 default:
1667 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1668 break;
1669 }
1670 }
1671
vmxnet3_get_command_status(VMXNET3State * s)1672 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1673 {
1674 uint64_t ret;
1675
1676 switch (s->last_command) {
1677 case VMXNET3_CMD_ACTIVATE_DEV:
1678 ret = (s->device_active) ? 0 : 1;
1679 VMW_CFPRN("Device active: %" PRIx64, ret);
1680 break;
1681
1682 case VMXNET3_CMD_RESET_DEV:
1683 case VMXNET3_CMD_QUIESCE_DEV:
1684 case VMXNET3_CMD_GET_QUEUE_STATUS:
1685 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1686 ret = 0;
1687 break;
1688
1689 case VMXNET3_CMD_GET_LINK:
1690 ret = s->link_status_and_speed;
1691 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1692 break;
1693
1694 case VMXNET3_CMD_GET_PERM_MAC_LO:
1695 ret = vmxnet3_get_mac_low(&s->perm_mac);
1696 break;
1697
1698 case VMXNET3_CMD_GET_PERM_MAC_HI:
1699 ret = vmxnet3_get_mac_high(&s->perm_mac);
1700 break;
1701
1702 case VMXNET3_CMD_GET_CONF_INTR:
1703 ret = vmxnet3_get_interrupt_config(s);
1704 break;
1705
1706 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1707 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1708 break;
1709
1710 case VMXNET3_CMD_GET_DID_LO:
1711 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1712 break;
1713
1714 case VMXNET3_CMD_GET_DID_HI:
1715 ret = VMXNET3_DEVICE_REVISION;
1716 break;
1717
1718 default:
1719 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1720 ret = 0;
1721 break;
1722 }
1723
1724 return ret;
1725 }
1726
vmxnet3_set_events(VMXNET3State * s,uint32_t val)1727 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1728 {
1729 uint32_t events;
1730 PCIDevice *d = PCI_DEVICE(s);
1731
1732 VMW_CBPRN("Setting events: 0x%x", val);
1733 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val;
1734 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
1735 }
1736
vmxnet3_ack_events(VMXNET3State * s,uint32_t val)1737 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1738 {
1739 PCIDevice *d = PCI_DEVICE(s);
1740 uint32_t events;
1741
1742 VMW_CBPRN("Clearing events: 0x%x", val);
1743 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val;
1744 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
1745 }
1746
1747 static void
vmxnet3_io_bar1_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)1748 vmxnet3_io_bar1_write(void *opaque,
1749 hwaddr addr,
1750 uint64_t val,
1751 unsigned size)
1752 {
1753 VMXNET3State *s = opaque;
1754
1755 switch (addr) {
1756 /* Vmxnet3 Revision Report Selection */
1757 case VMXNET3_REG_VRRS:
1758 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1759 val, size);
1760 break;
1761
1762 /* UPT Version Report Selection */
1763 case VMXNET3_REG_UVRS:
1764 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1765 val, size);
1766 break;
1767
1768 /* Driver Shared Address Low */
1769 case VMXNET3_REG_DSAL:
1770 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1771 val, size);
1772 /*
1773 * Guest driver will first write the low part of the shared
1774 * memory address. We save it to temp variable and set the
1775 * shared address only after we get the high part
1776 */
1777 if (val == 0) {
1778 vmxnet3_deactivate_device(s);
1779 }
1780 s->temp_shared_guest_driver_memory = val;
1781 s->drv_shmem = 0;
1782 break;
1783
1784 /* Driver Shared Address High */
1785 case VMXNET3_REG_DSAH:
1786 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1787 val, size);
1788 /*
1789 * Set the shared memory between guest driver and device.
1790 * We already should have low address part.
1791 */
1792 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1793 break;
1794
1795 /* Command */
1796 case VMXNET3_REG_CMD:
1797 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1798 val, size);
1799 vmxnet3_handle_command(s, val);
1800 break;
1801
1802 /* MAC Address Low */
1803 case VMXNET3_REG_MACL:
1804 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1805 val, size);
1806 s->temp_mac = val;
1807 break;
1808
1809 /* MAC Address High */
1810 case VMXNET3_REG_MACH:
1811 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1812 val, size);
1813 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1814 break;
1815
1816 /* Interrupt Cause Register */
1817 case VMXNET3_REG_ICR:
1818 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1819 val, size);
1820 qemu_log_mask(LOG_GUEST_ERROR,
1821 "%s: write to read-only register VMXNET3_REG_ICR\n",
1822 TYPE_VMXNET3);
1823 break;
1824
1825 /* Event Cause Register */
1826 case VMXNET3_REG_ECR:
1827 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1828 val, size);
1829 vmxnet3_ack_events(s, val);
1830 break;
1831
1832 default:
1833 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1834 addr, val, size);
1835 break;
1836 }
1837 }
1838
1839 static uint64_t
vmxnet3_io_bar1_read(void * opaque,hwaddr addr,unsigned size)1840 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1841 {
1842 VMXNET3State *s = opaque;
1843 uint64_t ret = 0;
1844
1845 switch (addr) {
1846 /* Vmxnet3 Revision Report Selection */
1847 case VMXNET3_REG_VRRS:
1848 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1849 ret = VMXNET3_DEVICE_REVISION;
1850 break;
1851
1852 /* UPT Version Report Selection */
1853 case VMXNET3_REG_UVRS:
1854 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1855 ret = VMXNET3_UPT_REVISION;
1856 break;
1857
1858 /* Command */
1859 case VMXNET3_REG_CMD:
1860 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1861 ret = vmxnet3_get_command_status(s);
1862 break;
1863
1864 /* MAC Address Low */
1865 case VMXNET3_REG_MACL:
1866 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1867 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1868 break;
1869
1870 /* MAC Address High */
1871 case VMXNET3_REG_MACH:
1872 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1873 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1874 break;
1875
1876 /*
1877 * Interrupt Cause Register
1878 * Used for legacy interrupts only so interrupt index always 0
1879 */
1880 case VMXNET3_REG_ICR:
1881 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1882 if (vmxnet3_interrupt_asserted(s, 0)) {
1883 vmxnet3_clear_interrupt(s, 0);
1884 ret = true;
1885 } else {
1886 ret = false;
1887 }
1888 break;
1889
1890 default:
1891 VMW_CBPRN("Unknown read BAR1[%" PRIx64 "], %d bytes", addr, size);
1892 break;
1893 }
1894
1895 return ret;
1896 }
1897
1898 static int
vmxnet3_can_receive(NetClientState * nc)1899 vmxnet3_can_receive(NetClientState *nc)
1900 {
1901 VMXNET3State *s = qemu_get_nic_opaque(nc);
1902 return s->device_active &&
1903 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1904 }
1905
1906 static inline bool
vmxnet3_is_registered_vlan(VMXNET3State * s,const void * data)1907 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1908 {
1909 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1910 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1911 return true;
1912 }
1913
1914 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1915 }
1916
1917 static bool
vmxnet3_is_allowed_mcast_group(VMXNET3State * s,const uint8_t * group_mac)1918 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1919 {
1920 int i;
1921 for (i = 0; i < s->mcast_list_len; i++) {
1922 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1923 return true;
1924 }
1925 }
1926 return false;
1927 }
1928
1929 static bool
vmxnet3_rx_filter_may_indicate(VMXNET3State * s,const void * data,size_t size)1930 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1931 size_t size)
1932 {
1933 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1934
1935 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1936 return true;
1937 }
1938
1939 if (!vmxnet3_is_registered_vlan(s, data)) {
1940 return false;
1941 }
1942
1943 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
1944 case ETH_PKT_UCAST:
1945 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1946 return false;
1947 }
1948 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1949 return false;
1950 }
1951 break;
1952
1953 case ETH_PKT_BCAST:
1954 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1955 return false;
1956 }
1957 break;
1958
1959 case ETH_PKT_MCAST:
1960 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1961 return true;
1962 }
1963 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1964 return false;
1965 }
1966 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1967 return false;
1968 }
1969 break;
1970
1971 default:
1972 g_assert_not_reached();
1973 }
1974
1975 return true;
1976 }
1977
1978 static ssize_t
vmxnet3_receive(NetClientState * nc,const uint8_t * buf,size_t size)1979 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1980 {
1981 VMXNET3State *s = qemu_get_nic_opaque(nc);
1982 size_t bytes_indicated;
1983
1984 if (!vmxnet3_can_receive(nc)) {
1985 VMW_PKPRN("Cannot receive now");
1986 return -1;
1987 }
1988
1989 if (s->peer_has_vhdr) {
1990 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1991 buf += sizeof(struct virtio_net_hdr);
1992 size -= sizeof(struct virtio_net_hdr);
1993 }
1994
1995 net_rx_pkt_set_packet_type(s->rx_pkt,
1996 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1997
1998 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
1999 struct iovec iov = {
2000 .iov_base = (void *)buf,
2001 .iov_len = size
2002 };
2003
2004 net_rx_pkt_set_protocols(s->rx_pkt, &iov, 1, 0);
2005 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
2006 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
2007 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
2008 if (bytes_indicated < size) {
2009 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
2010 }
2011 } else {
2012 VMW_PKPRN("Packet dropped by RX filter");
2013 bytes_indicated = size;
2014 }
2015
2016 assert(size > 0);
2017 assert(bytes_indicated != 0);
2018 return bytes_indicated;
2019 }
2020
vmxnet3_set_link_status(NetClientState * nc)2021 static void vmxnet3_set_link_status(NetClientState *nc)
2022 {
2023 VMXNET3State *s = qemu_get_nic_opaque(nc);
2024
2025 if (nc->link_down) {
2026 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2027 } else {
2028 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2029 }
2030
2031 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2032 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2033 }
2034
2035 static NetClientInfo net_vmxnet3_info = {
2036 .type = NET_CLIENT_DRIVER_NIC,
2037 .size = sizeof(NICState),
2038 .receive = vmxnet3_receive,
2039 .link_status_changed = vmxnet3_set_link_status,
2040 };
2041
vmxnet3_peer_has_vnet_hdr(VMXNET3State * s)2042 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2043 {
2044 NetClientState *nc = qemu_get_queue(s->nic);
2045
2046 if (qemu_has_vnet_hdr(nc->peer)) {
2047 return true;
2048 }
2049
2050 return false;
2051 }
2052
vmxnet3_net_uninit(VMXNET3State * s)2053 static void vmxnet3_net_uninit(VMXNET3State *s)
2054 {
2055 g_free(s->mcast_list);
2056 vmxnet3_deactivate_device(s);
2057 qemu_del_nic(s->nic);
2058 }
2059
vmxnet3_net_init(VMXNET3State * s)2060 static void vmxnet3_net_init(VMXNET3State *s)
2061 {
2062 DeviceState *d = DEVICE(s);
2063
2064 VMW_CBPRN("vmxnet3_net_init called...");
2065
2066 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2067
2068 /* Windows guest will query the address that was set on init */
2069 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2070
2071 s->mcast_list = NULL;
2072 s->mcast_list_len = 0;
2073
2074 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2075
2076 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
2077
2078 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2079 object_get_typename(OBJECT(s)),
2080 d->id, &d->mem_reentrancy_guard, s);
2081
2082 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2083 s->tx_sop = true;
2084 s->skip_current_tx_pkt = false;
2085 s->tx_pkt = NULL;
2086 s->rx_pkt = NULL;
2087 s->rx_vlan_stripping = false;
2088 s->lro_supported = false;
2089
2090 if (s->peer_has_vhdr) {
2091 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
2092 sizeof(struct virtio_net_hdr));
2093 }
2094
2095 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2096 }
2097
2098 static void
vmxnet3_unuse_msix_vectors(VMXNET3State * s,int num_vectors)2099 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2100 {
2101 PCIDevice *d = PCI_DEVICE(s);
2102 int i;
2103 for (i = 0; i < num_vectors; i++) {
2104 msix_vector_unuse(d, i);
2105 }
2106 }
2107
2108 static void
vmxnet3_use_msix_vectors(VMXNET3State * s,int num_vectors)2109 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2110 {
2111 PCIDevice *d = PCI_DEVICE(s);
2112 int i;
2113 for (i = 0; i < num_vectors; i++) {
2114 msix_vector_use(d, i);
2115 }
2116 }
2117
2118 static bool
vmxnet3_init_msix(VMXNET3State * s)2119 vmxnet3_init_msix(VMXNET3State *s)
2120 {
2121 PCIDevice *d = PCI_DEVICE(s);
2122 int res = msix_init(d, VMXNET3_MAX_INTRS,
2123 &s->msix_bar,
2124 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2125 &s->msix_bar,
2126 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
2127 VMXNET3_MSIX_OFFSET(s), NULL);
2128
2129 if (0 > res) {
2130 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2131 s->msix_used = false;
2132 } else {
2133 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS);
2134 s->msix_used = true;
2135 }
2136 return s->msix_used;
2137 }
2138
2139 static void
vmxnet3_cleanup_msix(VMXNET3State * s)2140 vmxnet3_cleanup_msix(VMXNET3State *s)
2141 {
2142 PCIDevice *d = PCI_DEVICE(s);
2143
2144 if (s->msix_used) {
2145 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2146 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2147 }
2148 }
2149
2150 static void
vmxnet3_cleanup_msi(VMXNET3State * s)2151 vmxnet3_cleanup_msi(VMXNET3State *s)
2152 {
2153 PCIDevice *d = PCI_DEVICE(s);
2154
2155 msi_uninit(d);
2156 }
2157
2158 static const MemoryRegionOps b0_ops = {
2159 .read = vmxnet3_io_bar0_read,
2160 .write = vmxnet3_io_bar0_write,
2161 .endianness = DEVICE_LITTLE_ENDIAN,
2162 .impl = {
2163 .min_access_size = 4,
2164 .max_access_size = 4,
2165 },
2166 };
2167
2168 static const MemoryRegionOps b1_ops = {
2169 .read = vmxnet3_io_bar1_read,
2170 .write = vmxnet3_io_bar1_write,
2171 .endianness = DEVICE_LITTLE_ENDIAN,
2172 .impl = {
2173 .min_access_size = 4,
2174 .max_access_size = 4,
2175 },
2176 };
2177
vmxnet3_device_serial_num(VMXNET3State * s)2178 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s)
2179 {
2180 uint64_t dsn_payload;
2181 uint8_t *dsnp = (uint8_t *)&dsn_payload;
2182
2183 dsnp[0] = 0xfe;
2184 dsnp[1] = s->conf.macaddr.a[3];
2185 dsnp[2] = s->conf.macaddr.a[4];
2186 dsnp[3] = s->conf.macaddr.a[5];
2187 dsnp[4] = s->conf.macaddr.a[0];
2188 dsnp[5] = s->conf.macaddr.a[1];
2189 dsnp[6] = s->conf.macaddr.a[2];
2190 dsnp[7] = 0xff;
2191 return dsn_payload;
2192 }
2193
2194
2195 #define VMXNET3_USE_64BIT (true)
2196 #define VMXNET3_PER_VECTOR_MASK (false)
2197
vmxnet3_pci_realize(PCIDevice * pci_dev,Error ** errp)2198 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2199 {
2200 VMXNET3State *s = VMXNET3(pci_dev);
2201 int ret;
2202
2203 VMW_CBPRN("Starting init...");
2204
2205 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2206 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2207 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2208 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2209
2210 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2211 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2212 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2213 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2214
2215 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2216 VMXNET3_MSIX_BAR_SIZE);
2217 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2218 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2219
2220 vmxnet3_reset_interrupt_states(s);
2221
2222 /* Interrupt pin A */
2223 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2224
2225 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
2226 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
2227 /* Any error other than -ENOTSUP(board's MSI support is broken)
2228 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2229 assert(!ret || ret == -ENOTSUP);
2230
2231 if (!vmxnet3_init_msix(s)) {
2232 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2233 }
2234
2235 vmxnet3_net_init(s);
2236
2237 if (pci_is_express(pci_dev)) {
2238 if (pci_bus_is_express(pci_get_bus(pci_dev))) {
2239 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
2240 }
2241
2242 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET,
2243 vmxnet3_device_serial_num(s));
2244 }
2245 }
2246
vmxnet3_instance_init(Object * obj)2247 static void vmxnet3_instance_init(Object *obj)
2248 {
2249 VMXNET3State *s = VMXNET3(obj);
2250 device_add_bootindex_property(obj, &s->conf.bootindex,
2251 "bootindex", "/ethernet-phy@0",
2252 DEVICE(obj));
2253 }
2254
vmxnet3_pci_uninit(PCIDevice * pci_dev)2255 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2256 {
2257 VMXNET3State *s = VMXNET3(pci_dev);
2258
2259 VMW_CBPRN("Starting uninit...");
2260
2261 vmxnet3_net_uninit(s);
2262
2263 vmxnet3_cleanup_msix(s);
2264
2265 vmxnet3_cleanup_msi(s);
2266 }
2267
vmxnet3_qdev_reset(DeviceState * dev)2268 static void vmxnet3_qdev_reset(DeviceState *dev)
2269 {
2270 PCIDevice *d = PCI_DEVICE(dev);
2271 VMXNET3State *s = VMXNET3(d);
2272
2273 VMW_CBPRN("Starting QDEV reset...");
2274 vmxnet3_reset(s);
2275 }
2276
vmxnet3_mc_list_needed(void * opaque)2277 static bool vmxnet3_mc_list_needed(void *opaque)
2278 {
2279 return true;
2280 }
2281
vmxnet3_mcast_list_pre_load(void * opaque)2282 static int vmxnet3_mcast_list_pre_load(void *opaque)
2283 {
2284 VMXNET3State *s = opaque;
2285
2286 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2287
2288 return 0;
2289 }
2290
2291
vmxnet3_pre_save(void * opaque)2292 static int vmxnet3_pre_save(void *opaque)
2293 {
2294 VMXNET3State *s = opaque;
2295
2296 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2297
2298 return 0;
2299 }
2300
2301 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2302 .name = "vmxnet3/mcast_list",
2303 .version_id = 1,
2304 .minimum_version_id = 1,
2305 .pre_load = vmxnet3_mcast_list_pre_load,
2306 .needed = vmxnet3_mc_list_needed,
2307 .fields = (const VMStateField[]) {
2308 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL,
2309 mcast_list_buff_size),
2310 VMSTATE_END_OF_LIST()
2311 }
2312 };
2313
2314 static const VMStateDescription vmstate_vmxnet3_ring = {
2315 .name = "vmxnet3-ring",
2316 .version_id = 0,
2317 .fields = (const VMStateField[]) {
2318 VMSTATE_UINT64(pa, Vmxnet3Ring),
2319 VMSTATE_UINT32(size, Vmxnet3Ring),
2320 VMSTATE_UINT32(cell_size, Vmxnet3Ring),
2321 VMSTATE_UINT32(next, Vmxnet3Ring),
2322 VMSTATE_UINT8(gen, Vmxnet3Ring),
2323 VMSTATE_END_OF_LIST()
2324 }
2325 };
2326
2327 static const VMStateDescription vmstate_vmxnet3_tx_stats = {
2328 .name = "vmxnet3-tx-stats",
2329 .version_id = 0,
2330 .fields = (const VMStateField[]) {
2331 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats),
2332 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats),
2333 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats),
2334 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats),
2335 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats),
2336 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats),
2337 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats),
2338 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats),
2339 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats),
2340 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats),
2341 VMSTATE_END_OF_LIST()
2342 }
2343 };
2344
2345 static const VMStateDescription vmstate_vmxnet3_txq_descr = {
2346 .name = "vmxnet3-txq-descr",
2347 .version_id = 0,
2348 .fields = (const VMStateField[]) {
2349 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2350 Vmxnet3Ring),
2351 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2352 Vmxnet3Ring),
2353 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr),
2354 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr),
2355 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats,
2356 struct UPT1_TxStats),
2357 VMSTATE_END_OF_LIST()
2358 }
2359 };
2360
2361 static const VMStateDescription vmstate_vmxnet3_rx_stats = {
2362 .name = "vmxnet3-rx-stats",
2363 .version_id = 0,
2364 .fields = (const VMStateField[]) {
2365 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats),
2366 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats),
2367 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats),
2368 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats),
2369 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats),
2370 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats),
2371 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats),
2372 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats),
2373 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats),
2374 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats),
2375 VMSTATE_END_OF_LIST()
2376 }
2377 };
2378
2379 static const VMStateDescription vmstate_vmxnet3_rxq_descr = {
2380 .name = "vmxnet3-rxq-descr",
2381 .version_id = 0,
2382 .fields = (const VMStateField[]) {
2383 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr,
2384 VMXNET3_RX_RINGS_PER_QUEUE, 0,
2385 vmstate_vmxnet3_ring, Vmxnet3Ring),
2386 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring,
2387 Vmxnet3Ring),
2388 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr),
2389 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr),
2390 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats,
2391 struct UPT1_RxStats),
2392 VMSTATE_END_OF_LIST()
2393 }
2394 };
2395
vmxnet3_post_load(void * opaque,int version_id)2396 static int vmxnet3_post_load(void *opaque, int version_id)
2397 {
2398 VMXNET3State *s = opaque;
2399
2400 net_tx_pkt_init(&s->tx_pkt, s->max_tx_frags);
2401 net_rx_pkt_init(&s->rx_pkt);
2402
2403 if (s->msix_used) {
2404 vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS);
2405 }
2406
2407 if (!vmxnet3_validate_queues(s)) {
2408 return -1;
2409 }
2410 vmxnet3_validate_interrupts(s);
2411
2412 return 0;
2413 }
2414
2415 static const VMStateDescription vmstate_vmxnet3_int_state = {
2416 .name = "vmxnet3-int-state",
2417 .version_id = 0,
2418 .fields = (const VMStateField[]) {
2419 VMSTATE_BOOL(is_masked, Vmxnet3IntState),
2420 VMSTATE_BOOL(is_pending, Vmxnet3IntState),
2421 VMSTATE_BOOL(is_asserted, Vmxnet3IntState),
2422 VMSTATE_END_OF_LIST()
2423 }
2424 };
2425
2426 static const VMStateDescription vmstate_vmxnet3 = {
2427 .name = "vmxnet3",
2428 .version_id = 1,
2429 .minimum_version_id = 1,
2430 .pre_save = vmxnet3_pre_save,
2431 .post_load = vmxnet3_post_load,
2432 .fields = (const VMStateField[]) {
2433 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2434 VMSTATE_MSIX(parent_obj, VMXNET3State),
2435 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2436 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2437 VMSTATE_BOOL(lro_supported, VMXNET3State),
2438 VMSTATE_UINT32(rx_mode, VMXNET3State),
2439 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2440 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2441 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2442 VMSTATE_UINT32(mtu, VMXNET3State),
2443 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2444 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2445 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2446 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2447 VMSTATE_UINT8(txq_num, VMXNET3State),
2448 VMSTATE_UINT8(rxq_num, VMXNET3State),
2449 VMSTATE_UINT32(device_active, VMXNET3State),
2450 VMSTATE_UINT32(last_command, VMXNET3State),
2451 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2452 VMSTATE_UINT32(temp_mac, VMXNET3State),
2453 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2454 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2455
2456 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State,
2457 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr,
2458 Vmxnet3TxqDescr),
2459 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State,
2460 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr,
2461 Vmxnet3RxqDescr),
2462 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State,
2463 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state,
2464 Vmxnet3IntState),
2465
2466 VMSTATE_END_OF_LIST()
2467 },
2468 .subsections = (const VMStateDescription * const []) {
2469 &vmxstate_vmxnet3_mcast_list,
2470 NULL
2471 }
2472 };
2473
2474 static Property vmxnet3_properties[] = {
2475 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2476 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
2477 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
2478 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
2479 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
2480 DEFINE_PROP_END_OF_LIST(),
2481 };
2482
vmxnet3_realize(DeviceState * qdev,Error ** errp)2483 static void vmxnet3_realize(DeviceState *qdev, Error **errp)
2484 {
2485 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
2486 PCIDevice *pci_dev = PCI_DEVICE(qdev);
2487 VMXNET3State *s = VMXNET3(qdev);
2488
2489 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
2490 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2491 }
2492
2493 vc->parent_dc_realize(qdev, errp);
2494 }
2495
vmxnet3_class_init(ObjectClass * class,void * data)2496 static void vmxnet3_class_init(ObjectClass *class, void *data)
2497 {
2498 DeviceClass *dc = DEVICE_CLASS(class);
2499 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2500 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
2501
2502 c->realize = vmxnet3_pci_realize;
2503 c->exit = vmxnet3_pci_uninit;
2504 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2505 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2506 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2507 c->romfile = "efi-vmxnet3.rom";
2508 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2509 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2510 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2511 device_class_set_parent_realize(dc, vmxnet3_realize,
2512 &vc->parent_dc_realize);
2513 dc->desc = "VMWare Paravirtualized Ethernet v3";
2514 device_class_set_legacy_reset(dc, vmxnet3_qdev_reset);
2515 dc->vmsd = &vmstate_vmxnet3;
2516 device_class_set_props(dc, vmxnet3_properties);
2517 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2518 }
2519
2520 static const TypeInfo vmxnet3_info = {
2521 .name = TYPE_VMXNET3,
2522 .parent = TYPE_PCI_DEVICE,
2523 .class_size = sizeof(VMXNET3Class),
2524 .instance_size = sizeof(VMXNET3State),
2525 .class_init = vmxnet3_class_init,
2526 .instance_init = vmxnet3_instance_init,
2527 .interfaces = (InterfaceInfo[]) {
2528 { INTERFACE_PCIE_DEVICE },
2529 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2530 { }
2531 },
2532 };
2533
vmxnet3_register_types(void)2534 static void vmxnet3_register_types(void)
2535 {
2536 VMW_CBPRN("vmxnet3_register_types called...");
2537 type_register_static(&vmxnet3_info);
2538 }
2539
2540 type_init(vmxnet3_register_types)
2541