/qemu/hw/net/ |
H A D | e1000e_core.c | 200 core->radv.core = core; in e1000e_intrmgr_initialize_all_timers() 201 core->rdtr.core = core; in e1000e_intrmgr_initialize_all_timers() 202 core->raid.core = core; in e1000e_intrmgr_initialize_all_timers() 203 core->tadv.core = core; in e1000e_intrmgr_initialize_all_timers() 204 core->tidv.core = core; in e1000e_intrmgr_initialize_all_timers() 206 core->itr.core = core; in e1000e_intrmgr_initialize_all_timers() 211 core->eitr[i].core = core; in e1000e_intrmgr_initialize_all_timers() 1771 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_ctrl() 2129 core->mac[ICS] = core->mac[ICR]; in e1000e_raise_interrupts() 2167 core->mac[ICS] = core->mac[ICR]; in e1000e_lower_interrupts() [all …]
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H A D | igb_core.c | 181 core->eitr[i].core = core; in igb_intrmgr_initialize_all_timers() 536 context.core = core; in igb_tx_pkt_switch() 740 if (core->mac[r->dh] <= core->mac[r->dt]) { in igb_ring_free_descr_num() 744 if (core->mac[r->dh] > core->mac[r->dt]) { in igb_ring_free_descr_num() 2087 igb_rx_fix_l4_csum(core, core->rx_pkt); in igb_receive_internal() 2137 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer); in igb_set_phy_ctrl() 2173 core->mac[CTRL_DUP] = core->mac[CTRL]; in igb_set_ctrl() 2356 if (!(core->mac[ICR] & core->mac[IMS]) && in igb_lower_interrupts() 3108 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); in igb_set_timadjh() 4473 memset(core->phy, 0, sizeof core->phy); in igb_reset() [all …]
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H A D | e1000e.c | 82 E1000ECore core; member 267 s->core.owner = &s->parent_obj; in e1000e_core_realize() 268 s->core.owner_nic = s->nic; in e1000e_core_realize() 328 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); in e1000e_init_net_peer() 334 s->core.has_vnet = false; in e1000e_init_net_peer() 338 s->core.has_vnet = true; in e1000e_init_net_peer() 344 s->core.has_vnet = false; in e1000e_init_net_peer() 407 e1000e_start_recv(&s->core); in e1000e_write_config() 492 e1000e_core_pci_realize(&s->core, in e1000e_pci_realize() 521 e1000e_core_reset(&s->core); in e1000e_qdev_reset_hold() [all …]
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H A D | igb_core.h | 63 IGBCore *core; member 108 igb_core_read(IGBCore *core, hwaddr addr, unsigned size); 117 igb_core_reset(IGBCore *core); 120 igb_core_pre_save(IGBCore *core); 123 igb_core_post_load(IGBCore *core); 126 igb_core_set_link_status(IGBCore *core); 129 igb_core_pci_uninit(IGBCore *core); 132 igb_core_vf_reset(IGBCore *core, uint16_t vfn); 135 igb_can_receive(IGBCore *core); 138 igb_receive(IGBCore *core, const uint8_t *buf, size_t size); [all …]
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H A D | e1000e_core.h | 58 E1000ECore *core; member 119 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size); 128 e1000e_core_reset(E1000ECore *core); 131 e1000e_core_pre_save(E1000ECore *core); 134 e1000e_core_post_load(E1000ECore *core); 137 e1000e_core_set_link_status(E1000ECore *core); 140 e1000e_core_pci_uninit(E1000ECore *core); 143 e1000e_can_receive(E1000ECore *core); 146 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size); 149 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt); [all …]
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H A D | igb.c | 80 IGBCore core; member 111 igb_start_recv(&s->core); in igb_write_config() 132 igb_core_vf_reset(&s->core, vfn); in igb_vf_reset() 288 s->core.owner = &s->parent_obj; in igb_core_realize() 289 s->core.owner_nic = s->nic; in igb_core_realize() 333 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); in igb_init_net_peer() 347 s->core.has_vnet = true; in igb_init_net_peer() 465 igb_core_pci_realize(&s->core, in igb_pci_realize() 477 igb_core_pci_uninit(&s->core); in igb_pci_uninit() 494 igb_core_reset(&s->core); in igb_qdev_reset_hold() [all …]
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/qemu/audio/ |
H A D | coreaudio.m | 401 core->audioDevicePropertyBufferFrameSize = core->frameSizeSetting; 428 core->hw.samples = core->bufferCount * core->audioDevicePropertyBufferFrameSize; 454 core->ioprocid = NULL; 485 status = AudioDeviceStop(core->outputDeviceID, core->ioprocid); 516 if (core->enabled) { 519 status = AudioDeviceStart(core->outputDeviceID, core->ioprocid); 547 if (core->outputDeviceID) { 548 fini_out_device(core); 595 if (init_out_device(core)) { 625 fini_out_device(core); [all …]
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/qemu/target/xtensa/ |
H A D | cores.list | 1 core-dc232b.c 2 core-dc233c.c 3 core-de212.c 4 core-de233_fpu.c 5 core-dsp3400.c 6 core-fsf.c 7 core-lx106.c 8 core-sample_controller.c 9 core-test_kc705_be.c 10 core-test_mmuhifi_c3.c
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H A D | import_core.sh | 7 TARGET="$BASE"/core-$NAME 10 Usage: $0 overlay-archive-to-import core-name [frequency-in-KHz] 13 core-name: QEMU name of the imported core. Must be valid 15 frequency-in-KHz: core frequency (40MHz if not specified). 23 xtensa/config/core-isa.h \ 24 xtensa/config/core-matmap.h 69 grep -qxf core-${NAME}.c "$BASE"/cores.list || \ 70 echo core-${NAME}.c >> "$BASE"/cores.list
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/qemu/include/hw/ppc/ |
H A D | pnv_xscom.h | 57 #define PNV_XSCOM_EX_BASE(core) \ argument 58 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) 91 #define PNV9_XSCOM_EC_BASE(core) \ argument 92 ((uint64_t)(((core) & 0x1F) + 0x20) << 24) 95 #define PNV9_XSCOM_EQ_BASE(core) \ argument 96 ((uint64_t)(((core) & 0x1C) + 0x40) << 22) 140 #define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) argument 152 #define PNV10_XSCOM_QME_BASE(core) \ argument 156 #define PNV10_XSCOM_EQ_BASE(core) \ argument 160 #define PNV10_XSCOM_EC_BASE(core) \ argument [all …]
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/qemu/hw/intc/ |
H A D | loongson_liointc.c | 64 uint32_t irq, core, ip; in update_irq() local 74 for (core = 0; core < NUM_CORES; core++) { in update_irq() 75 p->per_core_isr[core] = 0; in update_irq() 84 for (core = 0; core < NUM_CORES; core++) { in update_irq() 85 if ((p->mapper[irq] & (1 << core))) { in update_irq() 86 p->per_core_isr[core] |= (1 << irq); in update_irq() 98 for (core = 0; core < NUM_CORES; core++) { in update_irq() 129 int core = offset / R_ISR_SIZE; in liointc_read() local 134 r = p->per_core_isr[core]; in liointc_read() 178 int core = offset / R_ISR_SIZE; in liointc_write() local [all …]
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H A D | bcm2836_control.c | 63 static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq, in deliver_local() argument 68 s->fiqsrc[core] |= (uint32_t)1 << irq; in deliver_local() 71 s->irqsrc[core] |= (uint32_t)1 << irq; in deliver_local() 113 /* handle local timer interrupts for this core */ in bcm2836_control_update() 124 /* handle mailboxes for this core */ in bcm2836_control_update() 140 static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq, in bcm2836_control_set_local_irq() argument 145 assert(core >= 0 && core < BCM2836_NCORES); in bcm2836_control_set_local_irq() 148 s->timerirqs[core] = deposit32(s->timerirqs[core], local_ir in bcm2836_control_set_local_irq() 158 bcm2836_control_set_local_irq0(void * opaque,int core,int level) bcm2836_control_set_local_irq0() argument 163 bcm2836_control_set_local_irq1(void * opaque,int core,int level) bcm2836_control_set_local_irq1() argument 168 bcm2836_control_set_local_irq2(void * opaque,int core,int level) bcm2836_control_set_local_irq2() argument 173 bcm2836_control_set_local_irq3(void * opaque,int core,int level) bcm2836_control_set_local_irq3() argument [all...] |
/qemu/hw/cpu/ |
H A D | core.c | 20 CPUCore *core = CPU_CORE(obj); in core_prop_get_core_id() local 21 int64_t value = core->core_id; in core_prop_get_core_id() 29 CPUCore *core = CPU_CORE(obj); in core_prop_set_core_id() local 41 core->core_id = value; in core_prop_set_core_id() 47 CPUCore *core = CPU_CORE(obj); in core_prop_get_nr_threads() local 48 int64_t value = core->nr_threads; in core_prop_get_nr_threads() 56 CPUCore *core = CPU_CORE(obj); in core_prop_set_nr_threads() local 63 core->nr_threads = value; in core_prop_set_nr_threads() 68 CPUCore *core = CPU_CORE(obj); in cpu_core_instance_init() local 76 core->nr_threads = current_machine->smp.threads; in cpu_core_instance_init()
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/qemu/hw/arm/ |
H A D | bcm2836.c | 31 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, in bcm283x_base_init() 95 if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) { in bcm2835_realize() 101 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ)); in bcm2835_realize() 103 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ)); in bcm2835_realize() 140 object_property_set_bool(OBJECT(&s_base->cpu[n].core), in bcm2836_realize() 144 if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) { in bcm2836_realize() 150 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ)); in bcm2836_realize() 155 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_PHYS, in bcm2836_realize() 157 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_VIRT, in bcm2836_realize() 159 qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_HYP, in bcm2836_realize() [all …]
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/qemu/docs/system/s390x/ |
H A D | cpu-topology.rst | 77 based on the core-id starting with core-0 at position 0 of socket-0, 93 -device gen16b-s390x-cpu,core-id=1,dedicated=true 119 (qemu) device_add gen16b-s390x-cpu,core-id=9 140 -device host-s390x-cpu,core-id=14 \ 146 (qemu) device_add gen16b-s390x-cpu,core-id=9 148 The core-id defines the placement of the core in the topology by 149 starting with core 0 in socket 0 up to maxcpus. 154 They will take the core-ids 0,1,2,3,4 156 to the guest in socket 0, with core-ids 0,1,2,3. 160 be placed in socket 3, with core-id 14 [all …]
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/qemu/tests/qtest/ |
H A D | pnv-xscom-test.c | 48 #define PNV_XSCOM_EX_BASE(core) \ argument 49 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) 50 #define PNV_XSCOM_P9_EC_BASE(core) \ argument 51 ((uint64_t)(((core) & 0x1F) + 0x20) << 24) 52 #define PNV_XSCOM_P10_EC_BASE(core) \ argument 53 ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \ 54 (0x1000 << (3 - (core & 0x3))))
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H A D | numa-test.c | 132 "-numa cpu,node-id=0,socket-id=1,core-id=0 " in pc_numa_cpu() 133 "-numa cpu,node-id=0,socket-id=1,core-id=1,thread-id=0 " in pc_numa_cpu() 134 "-numa cpu,node-id=1,socket-id=1,core-id=1,thread-id=1"); in pc_numa_cpu() 141 int64_t socket, core, thread, node; in pc_numa_cpu() local 151 g_assert(qdict_haskey(props, "core-id")); in pc_numa_cpu() 152 core = qdict_get_int(props, "core-id"); in pc_numa_cpu() 158 } else if (socket == 1 && core == 0) { in pc_numa_cpu() 160 } else if (socket == 1 && core == 1 && thread == 0) { in pc_numa_cpu() 162 } else if (socket == 1 && core in pc_numa_cpu() 194 int64_t core, node; spapr_numa_cpu() local 238 int64_t socket, cluster, core, thread, node; aarch64_numa_cpu() local 288 int64_t socket, core, thread, node; loongarch64_numa_cpu() local [all...] |
/qemu/docs/devel/ |
H A D | s390-cpu-topology.rst | 16 -device z14-s390x-cpu,core-id=19,entitlement=high \ 17 -device z14-s390x-cpu,core-id=11,entitlement=low \ 18 -device z14-s390x-cpu,core-id=12,entitlement=high \ 36 "core-id": 0, 51 "core-id": 19, 66 "core-id": 11, 81 "core-id": 12, 106 "core-id": 11, 116 The core-id parameter is the only mandatory parameter and every
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/qemu/docs/devel/migration/ |
H A D | virtio.rst | 15 - virtio core, for common fields like features, number of queues, ... 34 virtio core virtio transport virtio device 71 virtio core virtio transport virtio device 108 load_device() procedure is invoked by the core before subsections have 114 added to the core for compatibility reasons. If transport or device specific 115 state is added, core needs to invoke a callback from the new subsection.
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/qemu/docs/system/ |
H A D | cpu-hotplug.rst | 40 "core-id": 0, 50 "core-id": 0, 65 (QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=1 core-id=0 thread-id=0 72 "core-id": 0, 98 "core-id": 0, 110 "core-id": 0,
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/qemu/configs/targets/ |
H A D | m68k-softmmu.mak | 3 TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml
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H A D | m68k-linux-user.mak | 5 TARGET_XML_FILES= gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-core.xml gdb-xml/m68k-fp.xml
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H A D | aarch64-softmmu.mak | 5 TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm…
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/qemu/docs/system/riscv/ |
H A D | shakti-c.rst | 7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C 8 is a 64bit RV64GCSUN processor core. 13 For more info on the Shakti C-class core, please see: 21 * 1 C-class core
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/qemu/docs/system/arm/ |
H A D | stellaris.rst | 7 - Cortex-M3 CPU core. 19 - Cortex-M3 CPU core.
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