/qemu/tcg/i386/ |
H A D | tcg-target.h | 113 #define have_bmi1 (cpuinfo & CPUINFO_BMI1) 114 #define have_avx1 (cpuinfo & CPUINFO_AVX1) 115 #define have_avx2 (cpuinfo & CPUINFO_AVX2) 116 #define have_movbe (cpuinfo & CPUINFO_MOVBE) 122 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ 123 (cpuinfo & CPUINFO_AVX512F)) 124 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) 125 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) 126 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) 198 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
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/qemu/tcg/ppc/ |
H A D | tcg-target.h | 66 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 67 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 68 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 69 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 70 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 71 #define have_vsx (cpuinfo & CPUINFO_VSX)
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/qemu/util/ |
H A D | cpuinfo-loongarch.c | 16 unsigned cpuinfo; variable 21 unsigned info = cpuinfo; in cpuinfo_init() 33 cpuinfo = info; in cpuinfo_init()
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H A D | cpuinfo-ppc.c | 16 unsigned cpuinfo; variable 21 unsigned info = cpuinfo; in cpuinfo_init() 62 cpuinfo = info; in cpuinfo_init()
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H A D | cpuinfo-aarch64.c | 24 unsigned cpuinfo; variable 50 unsigned info = cpuinfo; in cpuinfo_init() 76 cpuinfo = info; in cpuinfo_init()
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H A D | cpuinfo-i386.c | 12 unsigned cpuinfo; variable 17 unsigned info = cpuinfo; in cpuinfo_init() 97 cpuinfo = info; in cpuinfo_init()
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H A D | meson.build | 123 util_ss.add(files('cpuinfo-aarch64.c')) 125 util_ss.add(files('cpuinfo-i386.c')) 127 util_ss.add(files('cpuinfo-loongarch.c')) 129 util_ss.add(files('cpuinfo-ppc.c'))
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/qemu/host/include/aarch64/host/ |
H A D | atomic128-ldst.h | 25 #define HAVE_ATOMIC128_RO (cpuinfo & CPUINFO_LSE2) 45 if (cpuinfo & CPUINFO_LSE2) { in atomic16_read_rw() 65 if (cpuinfo & CPUINFO_LSE2) { in atomic16_set()
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H A D | cpuinfo.h | 17 extern unsigned cpuinfo;
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H A D | load-extract-al16-al8.h.inc | 11 #include "host/cpuinfo.h"
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/qemu/tcg/aarch64/ |
H A D | tcg-target.h | 65 #define have_lse (cpuinfo & CPUINFO_LSE) 66 #define have_lse2 (cpuinfo & CPUINFO_LSE2)
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/qemu/tcg/loongarch64/ |
H A D | tcg-target.h | 170 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) 175 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX)
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/qemu/host/include/loongarch64/host/ |
H A D | cpuinfo.h | 13 extern unsigned cpuinfo;
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H A D | atomic128-ldst.h | 15 #define HAVE_ATOMIC128_RO likely(cpuinfo & CPUINFO_LSX)
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H A D | load-extract-al16-al8.h.inc | 11 #include "host/cpuinfo.h"
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/qemu/host/include/ppc/host/ |
H A D | cpuinfo.h | 22 extern unsigned cpuinfo;
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/qemu/host/include/i386/host/ |
H A D | cpuinfo.h | 29 extern unsigned cpuinfo;
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/qemu/host/include/i386/host/crypto/ |
H A D | clmul.h | 16 # define HAVE_CLMUL_ACCEL likely(cpuinfo & CPUINFO_PCLMUL)
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H A D | aes-round.h | 16 # define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES)
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/qemu/host/include/aarch64/host/crypto/ |
H A D | clmul.h | 19 # define HAVE_CLMUL_ACCEL likely(cpuinfo & CPUINFO_PMULL)
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H A D | aes-round.h | 15 # define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_AES)
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/qemu/host/include/x86_64/host/ |
H A D | atomic128-ldst.h | 30 #define HAVE_ATOMIC128_RO likely(cpuinfo & CPUINFO_ATOMIC_VMOVDQA)
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H A D | load-extract-al16-al8.h.inc | 37 if ((cpuinfo & CPUINFO_ATOMIC_VMOVDQU) || (pi & 8)) {
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/qemu/host/include/ppc/host/crypto/ |
H A D | aes-round.h | 15 # define HAVE_AES_ACCEL likely(cpuinfo & CPUINFO_CRYPTO)
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/qemu/docs/system/ |
H A D | cpu-models-x86.rst.inc | 184 so it will not appear in the Linux ``/proc/cpuinfo`` in the host or 196 ``/proc/cpuinfo`` in the host or guest. 218 up in the Linux ``/proc/cpuinfo`` in the host or guest. 222 ``/proc/cpuinfo``; or (b) the
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