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Searched refs:cxl (Results 1 – 22 of 22) sorted by relevance

/qemu/docs/system/devices/
H A Dcxl.rst311 -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \
312 -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G
322 -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G
333 -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G
352 -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \
359 …-M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-gran…
378 -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \
380 -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \
382 -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \
384 -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \
[all …]
/qemu/hw/cxl/
H A Dmeson.build3 'cxl-component-utils.c',
4 'cxl-device-utils.c',
5 'cxl-mailbox-utils.c',
6 'cxl-host.c',
7 'cxl-cdat.c',
8 'cxl-events.c',
12 'cxl-host-stubs.c',
H A Dcxl-component-utils.c372 void cxl_component_create_dvsec(CXLComponentState *cxl, in cxl_component_create_dvsec() argument
376 PCIDevice *pdev = cxl->pdev; in cxl_component_create_dvsec()
377 uint16_t offset = cxl->dvsec_offset; in cxl_component_create_dvsec()
480 range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); in cxl_component_create_dvsec()
481 cxl->dvsec_offset += length; in cxl_component_create_dvsec()
/qemu/qapi/
H A Dcxl.json32 # @cxl-inject-general-media-event:
83 # @cxl-inject-dram-event:
144 # @cxl-inject-memory-module-event:
197 # @cxl-inject-poison:
214 { 'command': 'cxl-inject-poison',
278 'cxl-ide-tx',
279 'cxl-ide-rx'
302 # @cxl-inject-uncorrectable-errors:
348 # @cxl-inject-correctable-error:
428 # @cxl-add-dynamic-capacity:
[all …]
H A Dqapi-schema.json83 { 'include': 'cxl.json' }
H A Dmeson.build34 'cxl',
H A Dmachine.json603 # @cxl-fmw: List of CXLFixedMemoryWindowOptions
608 'data': { 'cxl-fmw': ['CXLFixedMemoryWindowOptions'] }
/qemu/hw/pci-bridge/
H A Dcxl_downstream.c95 static void build_dvsecs(CXLComponentState *cxl) in build_dvsecs() argument
100 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, in build_dvsecs()
111 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, in build_dvsecs()
121 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, in build_dvsecs()
130 cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, in build_dvsecs()
H A Dcxl_root_port.c106 static void build_dvsecs(CXLComponentState *cxl) in build_dvsecs() argument
111 cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, in build_dvsecs()
121 cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, in build_dvsecs()
131 cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, in build_dvsecs()
141 cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, in build_dvsecs()
H A Dpci_expander_bridge.c182 CXLHost *cxl = PXB_CXL_HOST(dev); in pxb_cxl_realize() local
183 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_realize()
200 CXLHost *cxl = pxb->cxl_host_bridge; in pxb_cxl_hook_up_registers() local
201 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_hook_up_registers()
286 CXLHost *cxl = PXB_CXL_DEV(dev)->cxl_host_bridge; in pxb_cxl_dev_reset() local
287 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_dev_reset()
288 PCIHostState *hb = PCI_HOST_BRIDGE(cxl); in pxb_cxl_dev_reset()
303 cxl->passthrough = true; in pxb_cxl_dev_reset()
H A Dcxl_upstream.c106 static void build_dvsecs(CXLComponentState *cxl) in build_dvsecs() argument
113 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, in build_dvsecs()
123 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, in build_dvsecs()
133 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, in build_dvsecs()
/qemu/hw/acpi/
H A Dcxl.c102 static void cedt_build_chbs(GArray *table_data, PXBCXLDev *cxl) in cedt_build_chbs() argument
104 PXBDev *pxb = PXB_DEV(cxl); in cedt_build_chbs()
105 SysBusDevice *sbd = SYS_BUS_DEVICE(cxl->cxl_host_bridge); in cedt_build_chbs()
H A Dmeson.build17 acpi_ss.add(when: 'CONFIG_ACPI_CXL', if_true: files('cxl.c'), if_false: files('cxl-stub.c'))
/qemu/hw/
H A Dmeson.build9 subdir('cxl') subdir
H A DKconfig9 source cxl/Kconfig
/qemu/scripts/coverity-scan/
H A DCOMPONENTS.md109 ~ .*/qemu(/include)?/hw/(cxl/|pci).*
/qemu/docs/system/
H A Ddevice-emulation.rst87 devices/cxl.rst
/qemu/docs/about/
H A Ddeprecated.rst319 ``-device cxl-type3,memdev=xxxx`` (since 8.0)
322 The ``cxl-type3`` device initially only used a single memory backend. With
/qemu/tests/qtest/
H A Dmeson.build40 (config_all_devices.has_key('CONFIG_CXL') ? ['cxl-test'] : [])
/qemu/hw/pci/
H A Dpci.c2645 ObjectClass *cxl = in pci_device_class_base_init() local
2647 assert(conventional || pcie || cxl); in pci_device_class_base_init()
/qemu/
H A Dqemu-options.hx42 …" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=s…
131 …``cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.…
161 …-machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interle…
H A DMAINTAINERS2929 F: hw/cxl/
2931 F: include/hw/cxl/
2932 F: qapi/cxl.json