| /qemu/hw/pci-bridge/ |
| H A D | cxl_downstream.c | 26 CXLComponentState cxl_cstate; member
38 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
39 uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
50 CXLComponentState *cxl_cstate = &dsp->cxl_cstate; in cxl_dsp_dvsec_write_config() local
52 if (range_contains(&cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { in cxl_dsp_dvsec_write_config()
54 addr -= cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC].lob; in cxl_dsp_dvsec_write_config()
142 CXLComponentState *cxl_cstate = &dsp->cxl_cstate; in cxl_dsp_realize() local
143 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_dsp_realize()
183 cxl_cstate->dvsec_offset = CXL_DOWNSTREAM_PORT_DVSEC_OFFSET; in cxl_dsp_realize()
184 cxl_cstate->pdev = d; in cxl_dsp_realize()
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| H A D | cxl_upstream.c | 37 return &usp->cxl_cstate; in cxl_usp_to_cstate()
47 addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob; in cxl_usp_dvsec_write_config()
142 CDATObject *cdat = &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat; in cxl_doe_cdat_rsp()
297 CXLComponentState *cxl_cstate = &usp->cxl_cstate; in cxl_usp_realize() local
298 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_usp_realize()
328 cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET; in cxl_usp_realize()
329 cxl_cstate->pdev = d; in cxl_usp_realize()
330 build_dvsecs(cxl_cstate); in cxl_usp_realize()
340 cxl_cstate->cdat.build_cdat_table = build_cdat_table; in cxl_usp_realize()
342 cxl_cstate->cdat.private = d; in cxl_usp_realize()
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| H A D | cxl_root_port.c | 49 CXLComponentState cxl_cstate; member
101 uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
102 uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
152 CXLComponentState *cxl_cstate = &crp->cxl_cstate; in cxl_rp_realize() local
153 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_rp_realize()
177 cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET; in cxl_rp_realize()
178 cxl_cstate->pdev = pci_dev; in cxl_rp_realize()
179 build_dvsecs(cxl_cstate); in cxl_rp_realize()
181 cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, in cxl_rp_realize()
222 if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { in cxl_rp_dvsec_write_config()
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| H A D | pci_expander_bridge.c | 63 return &host->cxl_cstate;
195 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_realize() local
196 struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; in pxb_cxl_realize()
198 cxl_component_register_block_init(OBJECT(dev), cxl_cstate, in pxb_cxl_realize()
213 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_hook_up_registers() local
214 struct MemoryRegion *mr = &cxl_cstate->crb.component_registers; in pxb_cxl_hook_up_registers()
299 CXLComponentState *cxl_cstate = &cxl->cxl_cstate; in pxb_cxl_dev_reset() local
301 uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers; in pxb_cxl_dev_reset()
302 uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask; in pxb_cxl_dev_reset()
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| /qemu/hw/cxl/ |
| H A D | switch-mailbox-cci.c | 29 CXLComponentState *cxl_cstate = &cswmb->cxl_cstate; in cswbcci_realize() local
41 cxl_cstate->dvsec_offset = 0x100; in cswbcci_realize()
42 cxl_cstate->pdev = pci_dev; in cswbcci_realize()
54 cxl_component_create_dvsec(cxl_cstate, CXL3_SWITCH_MAILBOX_CCI, in cswbcci_realize()
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| H A D | cxl-component-utils.c | 67 CXLComponentState *cxl_cstate = opaque; in cxl_cache_mem_read_reg() local
68 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_cache_mem_read_reg()
73 return cregs->special_ops->read(cxl_cstate, offset, 4); in cxl_cache_mem_read_reg()
91 static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, in dumb_hdm_handler() argument
94 ComponentRegisters *cregs = &cxl_cstate->crb; in dumb_hdm_handler()
124 CXLComponentState *cxl_cstate = opaque; in cxl_cache_mem_write_reg() local
125 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_cache_mem_write_reg()
137 cregs->special_ops->write(cxl_cstate, offset, value, size); in cxl_cache_mem_write_reg()
143 dumb_hdm_handler(cxl_cstate, offset, value); in cxl_cache_mem_write_reg()
191 CXLComponentState *cxl_cstate, in cxl_component_register_block_init() argument
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| H A D | cxl-cdat.c | 192 bool cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp) in cxl_doe_cdat_init() argument
194 CDATObject *cdat = &cxl_cstate->cdat; in cxl_doe_cdat_init()
203 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp) in cxl_doe_cdat_update() argument
205 CDATObject *cdat = &cxl_cstate->cdat; in cxl_doe_cdat_update()
212 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate) in cxl_doe_cdat_release() argument
214 CDATObject *cdat = &cxl_cstate->cdat; in cxl_doe_cdat_release()
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| /qemu/hw/mem/ |
| H A D | cxl_type3.c | 321 CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; in build_dvsecs() local
495 CXLComponentState *cxl_cstate = opaque; in ct3d_reg_write() local
497 CXLType3Dev *ct3d = container_of(cxl_cstate, CXLType3Dev, cxl_cstate); in ct3d_reg_write()
842 CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; in ct3_realize() local
863 cxl_cstate->dvsec_offset = 0x100; in ct3_realize()
866 ct3d->cxl_cstate.pdev = pci_dev; in ct3_realize()
900 cxl_cstate->cdat.private = ct3d; in ct3_realize()
901 if (!cxl_doe_cdat_init(cxl_cstate, errp)) { in ct3_realize()
937 cxl_doe_cdat_release(cxl_cstate); in ct3_realize()
957 CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; in ct3_exit() local
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| /qemu/include/hw/cxl/ |
| H A D | cxl_component.h | 254 CXLComponentState *cxl_cstate,
260 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate,
276 bool cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp);
277 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate);
278 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp);
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| H A D | cxl.h | 52 CXLComponentState cxl_cstate; member
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| H A D | cxl_device.h | 553 CXLComponentState cxl_cstate; member
628 CXLComponentState cxl_cstate; member
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| /qemu/include/hw/pci-bridge/ |
| H A D | cxl_upstream_port.h | 13 CXLComponentState cxl_cstate; member
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