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Searched refs:env (Results 1 – 25 of 738) sorted by relevance

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/qemu/linux-user/xtensa/
H A Dcpu_loop.c29 env->pc = env->sregs[EPC1]; in xtensa_rfw()
46 put_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_overflow4()
47 put_user_ual(env->regs[1], env->regs[5] - 12); in xtensa_overflow4()
48 put_user_ual(env->regs[2], env->regs[5] - 8); in xtensa_overflow4()
49 put_user_ual(env->regs[3], env->regs[5] - 4); in xtensa_overflow4()
55 get_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_underflow4()
56 get_user_ual(env->regs[1], env->regs[5] - 12); in xtensa_underflow4()
57 get_user_ual(env->regs[2], env->regs[5] - 8); in xtensa_underflow4()
58 get_user_ual(env->regs[3], env->regs[5] - 4); in xtensa_underflow4()
64 put_user_ual(env->regs[0], env->regs[9] - 16); in xtensa_overflow8()
[all …]
/qemu/target/sparc/
H A Dwin_helper.c42 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp()
43 memcpy32(env->regbase, env->regbase + env->nwindows * 16); in cpu_set_cwp()
49 memcpy32(env->regbase + env->nwindows * 16, env->regbase); in cpu_set_cwp()
144 cwp = cpu_cwp_inc(env, env->cwp + 1) ; in helper_rett()
149 env->psrs = env->psrps; in helper_rett()
158 cwp = cpu_cwp_dec(env, env->cwp - 1); in helper_save()
169 cwp = cpu_cwp_inc(env, env->cwp + 1); in helper_restore()
200 cwp = cpu_cwp_dec(env, env->cwp - 1); in helper_save()
361 dst = get_gl_gregset(env, env->gl); in cpu_gl_switch_gregs()
444 env->hpstate = env->htstate[env->tl]; in helper_done()
[all …]
H A Dint64_helper.c178 if (env->tl >= env->maxtl) { in sparc_cpu_do_interrupt()
184 if (env->tl < env->maxtl - 1) { in sparc_cpu_do_interrupt()
188 if (env->tl < env->maxtl) { in sparc_cpu_do_interrupt()
200 env->htstate[env->tl] = env->hpstate; in sparc_cpu_do_interrupt()
209 cpu_gl_switch_gregs(env, env->gl + 1); in sparc_cpu_do_interrupt()
241 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); in sparc_cpu_do_interrupt()
243 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); in sparc_cpu_do_interrupt()
245 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); in sparc_cpu_do_interrupt()
251 env->pc = env->tbr & ~0x7fffULL; in sparc_cpu_do_interrupt()
254 env->npc = env->pc + 4; in sparc_cpu_do_interrupt()
[all …]
/qemu/target/i386/
H A Dhelper.h4 DEF_HELPER_3(write_eflags, void, env, tl, i32)
5 DEF_HELPER_1(read_eflags, tl, env)
6 DEF_HELPER_2(divb_AL, void, env, tl)
7 DEF_HELPER_2(idivb_AL, void, env, tl)
8 DEF_HELPER_2(divw_AX, void, env, tl)
9 DEF_HELPER_2(idivw_AX, void, env, tl)
10 DEF_HELPER_2(divl_EAX, void, env, tl)
11 DEF_HELPER_2(idivl_EAX, void, env, tl)
13 DEF_HELPER_2(divq_EAX, void, env, tl)
14 DEF_HELPER_2(idivq_EAX, void, env, t
[all...]
H A Dmachine.c222 CPUX86State *env = &cpu->env; in cpu_pre_save() local
224 env->v_tpr = env->int_ctl & V_TPR_MASK; in cpu_pre_save()
226 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; in cpu_pre_save()
227 env->fptag_vmstate = 0; in cpu_pre_save()
229 env->fptag_vmstate |= ((!env in cpu_pre_save()
317 CPUX86State *env = &cpu->env; cpu_post_load() local
439 CPUX86State *env = &cpu->env; exception_info_needed() local
531 CPUX86State *env = &cpu->env; fpop_ip_dp_needed() local
552 CPUX86State *env = &cpu->env; tsc_adjust_needed() local
571 CPUX86State *env = &cpu->env; msr_smi_count_needed() local
590 CPUX86State *env = &cpu->env; tscdeadline_needed() local
609 CPUX86State *env = &cpu->env; misc_enable_needed() local
617 CPUX86State *env = &cpu->env; feature_control_needed() local
647 CPUX86State *env = &cpu->env; pmu_enable_needed() local
688 CPUX86State *env = &cpu->env; mpx_needed() local
721 CPUX86State *env = &cpu->env; hyperv_hypercall_enable_needed() local
741 CPUX86State *env = &cpu->env; hyperv_vapic_enable_needed() local
760 CPUX86State *env = &cpu->env; hyperv_time_enable_needed() local
779 CPUX86State *env = &cpu->env; hyperv_crash_enable_needed() local
804 CPUX86State *env = &cpu->env; hyperv_runtime_enable_needed() local
827 CPUX86State *env = &cpu->env; hyperv_synic_enable_needed() local
870 CPUX86State *env = &cpu->env; hyperv_stimer_enable_needed() local
897 CPUX86State *env = &cpu->env; hyperv_reenlightenment_enable_needed() local
907 CPUX86State *env = &cpu->env; hyperv_reenlightenment_post_load() local
940 CPUX86State *env = &cpu->env; avx512_needed() local
986 CPUX86State *env = &cpu->env; xss_needed() local
1005 CPUX86State *env = &cpu->env; umwait_needed() local
1024 CPUX86State *env = &cpu->env; pkru_needed() local
1043 CPUX86State *env = &cpu->env; pkrs_needed() local
1062 CPUX86State *env = &cpu->env; tsc_khz_needed() local
1177 CPUX86State *env = &cpu->env; nested_state_needed() local
1187 CPUX86State *env = &cpu->env; nested_state_post_load() local
1289 CPUX86State *env = &cpu->env; mcg_ext_ctl_needed() local
1307 CPUX86State *env = &cpu->env; spec_ctrl_needed() local
1327 CPUX86State *env = &cpu->env; amd_tsc_scale_msr_needed() local
1347 CPUX86State *env = &cpu->env; intel_pt_enable_needed() local
1384 CPUX86State *env = &cpu->env; virt_ssbd_needed() local
1403 CPUX86State *env = &cpu->env; svm_npt_needed() local
1423 CPUX86State *env = &cpu->env; svm_guest_needed() local
1443 CPUX86State *env = &cpu->env; intel_efer32_needed() local
1463 CPUX86State *env = &cpu->env; msr_tsx_ctrl_needed() local
1482 CPUX86State *env = &cpu->env; intel_sgx_msrs_needed() local
1501 CPUX86State *env = &cpu->env; pdptrs_needed() local
1508 CPUX86State *env = &cpu->env; pdptrs_post_load() local
1529 CPUX86State *env = &cpu->env; xfd_msrs_needed() local
1550 CPUX86State *env = &cpu->env; amx_xtile_needed() local
1571 CPUX86State *env = &cpu->env; arch_lbr_needed() local
1592 CPUX86State *env = &cpu->env; triple_fault_needed() local
[all...]
/qemu/target/i386/tcg/sysemu/
H A Dsvm_helper.c30 static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_save_seg() argument
33 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_save_seg()
35 cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_save_seg()
37 cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), in svm_save_seg()
39 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), in svm_save_seg()
49 static inline void svm_canonicalization(CPUX86State *env, target_ulong *seg_base) in svm_canonicalization() argument
51 uint16_t shift_amt = 64 - cpu_x86_virtual_addr_width(env); in svm_canonicalization()
55 static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_load_seg() argument
61 cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_load_seg()
64 cpu_ldq_mmuidx_ra(env, add in svm_load_seg()
77 svm_load_seg_cache(CPUX86State * env,int mmu_idx,hwaddr addr,int seg_reg) svm_load_seg_cache() argument
87 is_efer_invalid_state(CPUX86State * env) is_efer_invalid_state() argument
122 virtual_gif_enabled(CPUX86State * env) virtual_gif_enabled() argument
131 virtual_vm_load_save_enabled(CPUX86State * env,uint32_t exit_code,uintptr_t retaddr) virtual_vm_load_save_enabled() argument
150 virtual_gif_set(CPUX86State * env) virtual_gif_set() argument
155 helper_vmrun(CPUX86State * env,int aflag,int next_eip_addend) helper_vmrun() argument
460 helper_vmmcall(CPUX86State * env) helper_vmmcall() argument
466 helper_vmload(CPUX86State * env,int aflag) helper_vmload() argument
527 helper_vmsave(CPUX86State * env,int aflag) helper_vmsave() argument
578 helper_stgi(CPUX86State * env) helper_stgi() argument
590 helper_clgi(CPUX86State * env) helper_clgi() argument
602 cpu_svm_has_intercept(CPUX86State * env,uint32_t type) cpu_svm_has_intercept() argument
639 cpu_svm_check_intercept_param(CPUX86State * env,uint32_t type,uint64_t param,uintptr_t retaddr) cpu_svm_check_intercept_param() argument
689 helper_svm_check_intercept(CPUX86State * env,uint32_t type) helper_svm_check_intercept() argument
694 helper_svm_check_io(CPUX86State * env,uint32_t port,uint32_t param,uint32_t next_eip_addend) helper_svm_check_io() argument
715 cpu_vmexit(CPUX86State * env,uint32_t exit_code,uint64_t exit_info_1,uintptr_t retaddr) cpu_vmexit() argument
741 do_vmexit(CPUX86State * env) do_vmexit() argument
[all...]
H A Dmisc_helper.c30 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) in helper_outb() argument
33 cpu_get_mem_attrs(env), NULL); in helper_outb()
36 target_ulong helper_inb(CPUX86State *env, uint32_t port) in helper_inb() argument
39 cpu_get_mem_attrs(env), NULL); in helper_inb()
42 void helper_outw(CPUX86State *env, uint32_t port, uint32_t data) in helper_outw() argument
45 cpu_get_mem_attrs(env), NULL); in helper_outw()
48 target_ulong helper_inw(CPUX86State *env, uint32_t port) in helper_inw() argument
51 cpu_get_mem_attrs(env), NULL); in helper_inw()
54 void helper_outl(CPUX86State *env, uint32_t port, uint32_t data) in helper_outl() argument
57 cpu_get_mem_attrs(env), NUL in helper_outl()
60 helper_inl(CPUX86State * env,uint32_t port) helper_inl() argument
66 helper_read_crN(CPUX86State * env,int reg) helper_read_crN() argument
85 helper_write_crN(CPUX86State * env,int reg,target_ulong t0) helper_write_crN() argument
141 helper_wrmsr(CPUX86State * env) helper_wrmsr() argument
338 helper_rdmsr(CPUX86State * env) helper_rdmsr() argument
514 helper_flush_page(CPUX86State * env,target_ulong addr) helper_flush_page() argument
520 do_hlt(CPUX86State * env) do_hlt() argument
530 helper_hlt(CPUX86State * env,int next_eip_addend) helper_hlt() argument
538 helper_monitor(CPUX86State * env,target_ulong ptr) helper_monitor() argument
547 helper_mwait(CPUX86State * env,int next_eip_addend) helper_mwait() argument
[all...]
/qemu/target/rx/
H A Dop_helper.c40 env->isp = env->regs[0]; in _set_psw()
41 env->regs[0] = env->usp; in _set_psw()
43 env->usp = env->regs[0]; in _set_psw()
44 env->regs[0] = env->isp; in _set_psw()
83 env->fpsw = FIELD_DP32(env->fpsw, FPSW, CAUSE, 0); in update_fpsw()
161 env->psw_s = env->psw_o = 0; in FLOATOP()
241 cpu_stfn[sz](env, env->regs[1], env->regs[2], GETPC()); in helper_sstr()
300 env->psw_z = tmp - env->regs[2]; in helper_suntil()
301 env->psw_c = (tmp <= env->regs[2]); in helper_suntil()
319 env->psw_z = env->regs[3]; in helper_swhile()
[all …]
/qemu/target/ppc/
H A Dexcp_helper.c294 CPUPPCState *env = &cpu->env; in ppc_excp_apply_ail() local
391 CPUPPCState *env = &cpu->env; in powerpc_reset_excp_state() local
401 CPUPPCState *env = &cpu->env; in powerpc_set_excp_state() local
484 CPUPPCState *env = &cpu->env; in powerpc_excp_40x() local
585 env->spr[srr0] = env->nip; in powerpc_excp_40x()
1208 env->spr[srr0] = env->nip; in powerpc_excp_booke()
1318 return is_prefix_insn(env, ppc_ldl_code(env, env->nip)); in is_prefix_insn_excp()
1494 env->lr = env->nip; in powerpc_excp_books()
2668 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); in helper_rfid()
2673 do_rfi(env, env->lr, env->ctr); in helper_rfscv()
[all …]
/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c37 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
49 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
409 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar()
487 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar()
1271 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()
1277 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1296 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar()
1301 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar()
1579 if (&other_cpu->env != env) { in helper_dvpe()
1595 if (&other_cpu->env != env in helper_evpe()
[all …]
H A Dtlb_helper.c275 env->tlb->helper_tlbwi(env); in helper_tlbwi()
280 env->tlb->helper_tlbwr(env); in helper_tlbwr()
285 env->tlb->helper_tlbp(env); in helper_tlbp()
290 env->tlb->helper_tlbr(env); in helper_tlbr()
295 env->tlb->helper_tlbinv(env); in helper_tlbinv()
300 env->tlb->helper_tlbinvf(env); in helper_tlbinvf()
562 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | in raise_mmu_exception()
566 env->CP0_EntryHi &= env->SEGMask; in raise_mmu_exception()
1020 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); in set_badinstr_registers()
1031 CPUMIPSState *env = &cpu->env; in mips_cpu_do_interrupt() local
[all …]
/qemu/target/riscv/
H A Dfpu_helper.c222 return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); in helper_fadd_s()
229 return nanbox_s(env, float32_sub(frs1, frs2, &env->fp_status)); in helper_fsub_s()
236 return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); in helper_fmul_s()
243 return nanbox_s(env, float32_div(frs1, frs2, &env->fp_status)); in helper_fdiv_s()
250 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmin_s()
267 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmax_s()
283 return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); in helper_fsqrt_s()
357 return nanbox_s(env, int64_to_float32(rs1, &env->fp_status)); in helper_fcvt_s_l()
583 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmin_h()
600 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmax_h()
[all …]
H A Dop_helper.c140 if ((env->priv < PRV_M) && !get_field(env->menvcfg, envbits)) { in check_zicbo_envcfg()
145 (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || in check_zicbo_envcfg()
146 ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { in check_zicbo_envcfg()
150 if ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)) { in check_zicbo_envcfg()
278 if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { in helper_sret()
282 if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { in helper_sret()
297 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret()
385 if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && in helper_wrs_nto()
399 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) { in helper_tlb_flush()
424 (env->priv == PRV_S && !env->virt_enabled)) { in helper_hyp_tlb_flush()
[all …]
/qemu/target/arm/tcg/
H A Dm_helper.c217 CPUARMState *env = &cpu->env; in v7m_stack_write() local
305 CPUARMState *env = &cpu->env; in v7m_stack_read() local
660 CPUARMState *env = &cpu->env; in arm_v7m_load_vector() local
764 CPUARMState *env = &cpu->env; in v7m_push_callee_stack() local
841 CPUARMState *env = &cpu->env; in v7m_exception_taken() local
1185 CPUARMState *env = &cpu->env; in v7m_push_stack() local
1359 CPUARMState *env = &cpu->env; in do_v7m_exception_exit() local
1917 CPUARMState *env = &cpu->env; in do_v7m_function_return() local
1994 CPUARMState *env = &cpu->env; in v7m_read_half_insn() local
2042 CPUARMState *env = &cpu->env; in v7m_read_sg_stack_word() local
[all …]
H A Dhelper-mve.h19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
32 DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32)
33 DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32)
217 DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env)
[all …]
/qemu/linux-user/sparc/
H A Dcpu_loop.c68 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & in save_window()
70 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); in save_window()
77 save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); in save_window()
92 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & in restore_window()
97 cwp1 = cpu_cwp_inc(env, env->cwp + 1); in restore_window()
114 if (env->cleanwin < env->nwindows - 1) in restore_window()
142 cwp1 = cpu_cwp_inc(env, env->cwp + 1); in flush_windows()
154 env->pc = env->npc; in next_instruction()
155 env->npc = env->npc + 4; in next_instruction()
243 env->pc = env->npc; in cpu_loop()
[all …]
/qemu/target/mips/
H A Dcpu.c90 env->hflags, env->btarget, env->bcond); in mips_cpu_dump_state()
104 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in mips_cpu_dump_state()
107 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); in mips_cpu_dump_state()
193 CPUMIPSState *env = &cpu->env; in mips_cpu_reset_hold() local
222 env->CCRes = env->cpu_model->CCRes; in mips_cpu_reset_hold()
253 env->msair = env->cpu_model->MSAIR; in mips_cpu_reset_hold()
450 CPUMIPSState *env = &cpu->env; in mips_cp0_period_set() local
461 CPUMIPSState *env = &cpu->env; in mips_cpu_realizefn() local
488 mmu_init(env, env->cpu_model); in mips_cpu_realizefn()
490 fpu_init(env, env->cpu_model); in mips_cpu_realizefn()
[all …]
/qemu/target/mips/tcg/
H A Dsysemu_helper.h.inc18 DEF_HELPER_1(mfc0_random, tl, env)
21 DEF_HELPER_1(mfc0_tcbind, tl, env)
37 DEF_HELPER_1(mftc0_epc, tl, env)
41 DEF_HELPER_1(mfc0_maar, tl, env)
147 DEF_HELPER_1(mftdsp, tl, env)
155 DEF_HELPER_1(dvpe, tl, env)
156 DEF_HELPER_1(evpe, tl, env)
159 DEF_HELPER_1(dvp, tl, env)
160 DEF_HELPER_1(evp, tl, env)
172 DEF_HELPER_1(di, tl, env)
[all …]
H A Dfpu_helper.c98 compute_hflags(env); in helper_ctc1()
110 compute_hflags(env); in helper_ctc1()
122 compute_hflags(env); in helper_ctc1()
134 compute_hflags(env); in helper_ctc1()
143 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | in helper_ctc1()
151 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | in helper_ctc1()
158 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | in helper_ctc1()
163 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) | in helper_ctc1()
164 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); in helper_ctc1()
172 restore_fp_status(env); in helper_ctc1()
[all …]
/qemu/target/xtensa/
H A Dexc_helper.c81 HELPER(debug_exception)(env, env->pc, cause); in debug_exception_env()
92 env->sregs[EPS2 + level - 2] = env->sregs[PS]; in HELPER()
105 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | in HELPER()
176 env->sregs[EPC1 + level - 1] = env->pc; in handle_interrupt()
180 env->pc = relocated_vector(env, in handle_interrupt()
190 env->sregs[DEPC] = env->pc; in handle_interrupt()
192 env->sregs[EPC1] = env->pc; in handle_interrupt()
196 env->sregs[EPC1] = env->pc; in handle_interrupt()
218 env->pc, env->regs[0], env->sregs[PS], in xtensa_cpu_do_interrupt()
238 env->pc, env->regs[0], env->sregs[PS], in xtensa_cpu_do_interrupt()
[all …]
H A Dwin_helper.c40 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
44 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
46 memcpy(env->regs + window + n1, env->phys_regs, in copy_window_from_phys()
56 memcpy(env->phys_regs + phys, env->regs + window, in copy_phys_from_window()
60 memcpy(env->phys_regs + phys, env->regs + window, in copy_phys_from_window()
62 memcpy(env->phys_regs, env->regs + window + n1, in copy_phys_from_window()
110 env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env); in HELPER()
123 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | in HELPER()
125 env->sregs[EPC1] = env->pc = pc; in HELPER()
173 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | in HELPER()
[all …]
/qemu/target/sh4/
H A Dop_helper.c54 cpu_load_tlb(env); in helper_ldtlb()
62 CPUState *cs = env_cpu(env); in raise_exception()
93 env->in_sleep = 1; in helper_sleep()
99 env->tra = tra << 2; in helper_trapa()
134 env->movcal_backup_tail = &(env->movcal_backup); in helper_discard_movcal_backup()
166 int64_t mac = env->mac; in helper_macl()
177 env->mac = res; in helper_macl()
196 env->mach = 1; in helper_macw()
198 env->macl = res; in helper_macw()
201 env->mac += mul; in helper_macw()
[all …]
/qemu/target/hppa/
H A Dgdbstub.c40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
115 val = env->cr[24]; in hppa_cpu_gdb_read_register()
118 val = env->cr[25]; in hppa_cpu_gdb_read_register()
121 val = env->cr[26]; in hppa_cpu_gdb_read_register()
124 val = env->cr[27]; in hppa_cpu_gdb_read_register()
127 val = env->cr[28]; in hppa_cpu_gdb_read_register()
160 env->gr[n] = val; in hppa_cpu_gdb_write_register()
163 env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31); in hppa_cpu_gdb_write_register()
[all …]
/qemu/target/m68k/
H A Dop_helper.c206 do_m68k_semihosting(env, env->dregs[0]); in cf_interrupt_all()
213 sr = env->sr | cpu_m68k_get_ccr(env); in cf_interrupt_all()
218 vector, env->pc, env->aregs[7], sr); in cf_interrupt_all()
227 env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); in cf_interrupt_all()
242 env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0); in cf_interrupt_all()
293 sr = env->sr | cpu_m68k_get_ccr(env); in m68k_interrupt_all()
298 vector, env->pc, env->aregs[7], sr); in m68k_interrupt_all()
379 env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); in m68k_interrupt_all()
395 do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); in m68k_interrupt_all()
420 env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
[all …]
/qemu/target/i386/tcg/
H A Dseg_helper.c31 int get_pg_mode(CPUX86State *env) in get_pg_mode() argument
34 if (!(env->cr[0] & CR0_PG_MASK)) { in get_pg_mode()
37 if (env->cr[0] & CR0_WP_MASK) { in get_pg_mode()
40 if (env->cr[4] & CR4_PAE_MASK) { in get_pg_mode()
42 if (env->efer & MSR_EFER_NXE) { in get_pg_mode()
46 if (env->cr[4] & CR4_PSE_MASK) { in get_pg_mode()
49 if (env->cr[4] & CR4_SMEP_MASK) { in get_pg_mode()
52 if (env->hflags & HF_LMA_MASK) { in get_pg_mode()
54 if (env->cr[4] & CR4_PKE_MASK) { in get_pg_mode()
57 if (env in get_pg_mode()
68 load_segment_ra(CPUX86State * env,uint32_t * e1_ptr,uint32_t * e2_ptr,int selector,uintptr_t retaddr) load_segment_ra() argument
91 load_segment(CPUX86State * env,uint32_t * e1_ptr,uint32_t * e2_ptr,int selector) load_segment() argument
122 load_seg_vm(CPUX86State * env,int seg,int selector) load_seg_vm() argument
131 get_ss_esp_from_tss(CPUX86State * env,uint32_t * ss_ptr,uint32_t * esp_ptr,int dpl,uintptr_t retaddr) get_ss_esp_from_tss() argument
173 tss_load_seg(CPUX86State * env,X86Seg seg_reg,int selector,int cpl,uintptr_t retaddr) tss_load_seg() argument
229 tss_set_busy(CPUX86State * env,int tss_selector,bool value,uintptr_t retaddr) tss_set_busy() argument
249 switch_tss_ra(CPUX86State * env,int tss_selector,uint32_t e1,uint32_t e2,int source,uint32_t next_eip,uintptr_t retaddr) switch_tss_ra() argument
508 switch_tss(CPUX86State * env,int tss_selector,uint32_t e1,uint32_t e2,int source,uint32_t next_eip) switch_tss() argument
599 do_interrupt_protected(CPUX86State * env,int intno,int is_int,int error_code,unsigned int next_eip,int is_hw) do_interrupt_protected() argument
831 get_rsp_from_tss(CPUX86State * env,int level) get_rsp_from_tss() argument
864 do_interrupt64(CPUX86State * env,int intno,int is_int,int error_code,target_ulong next_eip,int is_hw) do_interrupt64() argument
983 helper_sysret(CPUX86State * env,int dflag) helper_sysret() argument
1040 do_interrupt_real(CPUX86State * env,int intno,int is_int,int error_code,unsigned int next_eip) do_interrupt_real() argument
1086 CPUX86State *env = &cpu->env; do_interrupt_all() local
1160 do_interrupt_x86_hardirq(CPUX86State * env,int intno,int is_hw) do_interrupt_x86_hardirq() argument
1165 helper_lldt(CPUX86State * env,int selector) helper_lldt() argument
1219 helper_ltr(CPUX86State * env,int selector) helper_ltr() argument
1283 helper_load_seg(CPUX86State * env,int seg_reg,int selector) helper_load_seg() argument
1371 helper_ljmp_protected(CPUX86State * env,int new_cs,target_ulong new_eip,target_ulong next_eip) helper_ljmp_protected() argument
1511 helper_lcall_real(CPUX86State * env,uint32_t new_cs,uint32_t new_eip,int shift,uint32_t next_eip) helper_lcall_real() argument
1535 helper_lcall_protected(CPUX86State * env,int new_cs,target_ulong new_eip,int shift,target_ulong next_eip) helper_lcall_protected() argument
1832 helper_iret_real(CPUX86State * env,int shift) helper_iret_real() argument
1871 validate_seg(CPUX86State * env,X86Seg seg_reg,int cpl) validate_seg() argument
1898 helper_ret_protected(CPUX86State * env,int shift,int is_iret,int addend,uintptr_t retaddr) helper_ret_protected() argument
2118 helper_iret_protected(CPUX86State * env,int shift,int next_eip) helper_iret_protected() argument
2149 helper_lret_protected(CPUX86State * env,int shift,int addend) helper_lret_protected() argument
2154 helper_sysenter(CPUX86State * env) helper_sysenter() argument
2187 helper_sysexit(CPUX86State * env,int dflag) helper_sysexit() argument
2226 helper_lsl(CPUX86State * env,target_ulong selector1) helper_lsl() argument
2274 helper_lar(CPUX86State * env,target_ulong selector1) helper_lar() argument
2323 helper_verr(CPUX86State * env,target_ulong selector1) helper_verr() argument
2361 helper_verw(CPUX86State * env,target_ulong selector1) helper_verw() argument
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