Searched refs:irq_enabled (Results 1 – 14 of 14) sorted by relevance
/qemu/hw/arm/ |
H A D | integratorcp.c | 53 uint32_t irq_enabled; member 130 return s->int_level & s->irq_enabled; in integratorcm_read() 134 return s->irq_enabled; in integratorcm_read() 229 s->irq_enabled |= value; in integratorcm_write() 233 s->irq_enabled &= ~value; in integratorcm_write() 336 uint32_t irq_enabled; member 358 flags = (s->level & s->irq_enabled); in icp_pic_update() 381 return s->level & s->irq_enabled; in icp_pic_read() 385 return s->irq_enabled; in icp_pic_read() 411 s->irq_enabled |= value; in icp_pic_write() [all …]
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/qemu/hw/i2c/ |
H A D | smbus_ich9.c | 39 bool irq_enabled; member 55 VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus), 87 if (enabled == s->irq_enabled) { in ich9_smb_set_irq() 91 s->irq_enabled = enabled; in ich9_smb_set_irq()
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/qemu/hw/rtc/ |
H A D | goldfish_rtc.c | 48 qemu_set_irq(s->irq, (s->irq_pending & s->irq_enabled) ? 1 : 0); in goldfish_rtc_update() 121 r = s->irq_enabled; in goldfish_rtc_read() 162 s->irq_enabled = (uint32_t)(value & 0x1); in goldfish_rtc_write() 250 VMSTATE_UINT32(irq_enabled, GoldfishRTCState), 271 s->irq_enabled = 0; in goldfish_rtc_reset()
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/qemu/hw/timer/ |
H A D | pxa2xx_timer.c | 103 uint32_t irq_enabled; member 234 return s->irq_enabled; in pxa2xx_timer_read() 339 s->irq_enabled = value & 0xfff; in pxa2xx_timer_write() 413 if (i->irq_enabled & (1 << t->num)) { in pxa2xx_timer_tick() 460 s->irq_enabled = 0; in pxa2xx_timer_init() 544 VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
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/qemu/include/hw/misc/ |
H A D | virt_ctrl.h | 21 uint32_t irq_enabled; member
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/qemu/include/hw/rtc/ |
H A D | goldfish_rtc.h | 43 uint32_t irq_enabled; member
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/qemu/hw/cxl/ |
H A D | cxl-events.c | 40 log->irq_enabled = false; in cxl_event_init() 251 if (!log->irq_enabled || cxl_event_empty(log)) { in cxl_event_irq_assert()
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H A D | cxl-mailbox-utils.c | 287 if (log->irq_enabled) { in cmd_events_get_interrupt_policy() 292 if (log->irq_enabled) { in cmd_events_get_interrupt_policy() 297 if (log->irq_enabled) { in cmd_events_get_interrupt_policy() 302 if (log->irq_enabled) { in cmd_events_get_interrupt_policy() 307 if (log->irq_enabled) { in cmd_events_get_interrupt_policy() 334 log->irq_enabled = (policy->info_settings & CXL_EVENT_INT_MODE_MASK) == in cmd_events_set_interrupt_policy() 338 log->irq_enabled = (policy->warn_settings & CXL_EVENT_INT_MODE_MASK) == in cmd_events_set_interrupt_policy() 342 log->irq_enabled = (policy->failure_settings & CXL_EVENT_INT_MODE_MASK) == in cmd_events_set_interrupt_policy() 346 log->irq_enabled = (policy->fatal_settings & CXL_EVENT_INT_MODE_MASK) == in cmd_events_set_interrupt_policy() 355 log->irq_enabled = (policy->dyn_cap_settings & CXL_EVENT_INT_MODE_MASK) == in cmd_events_set_interrupt_policy()
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/qemu/hw/misc/ |
H A D | virt_ctrl.c | 112 VMSTATE_UINT32(irq_enabled, VirtCtrlState),
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/qemu/hw/ipmi/ |
H A D | pci_ipmi_bt.c | 37 bool irq_enabled; member
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H A D | pci_ipmi_kcs.c | 37 bool irq_enabled; member
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/qemu/hw/nvme/ |
H A D | nvme.h | 500 uint16_t irq_enabled; member
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H A D | ctrl.c | 666 if (cq->irq_enabled) { in nvme_irq_assert() 683 if (cq->irq_enabled) { in nvme_irq_deassert() 1525 if (cq->irq_enabled && !pending) { in nvme_post_cqes() 4675 if (cq->irq_enabled) { in nvme_cq_notifier() 5424 if (cq->irq_enabled && cq->tail != cq->head) { in nvme_del_cq() 5436 uint16_t irq_enabled) in nvme_init_cq() argument 5448 cq->irq_enabled = irq_enabled; in nvme_init_cq() 7874 if (cq->irq_enabled) { in nvme_process_db()
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/qemu/include/hw/cxl/ |
H A D | cxl_device.h | 160 bool irq_enabled; member
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