Searched refs:masks (Results 1 – 10 of 10) sorted by relevance
/qemu/include/hw/s390x/ |
H A D | event-facility.h | 57 uint8_t masks[]; member 68 #define WEM_CP_RECEIVE_MASK(wem, mask_len) ((wem)->masks) 69 #define WEM_CP_SEND_MASK(wem, mask_len) ((wem)->masks + (mask_len)) 70 #define WEM_RECEIVE_MASK(wem, mask_len) ((wem)->masks + 2 * (mask_len)) 71 #define WEM_SEND_MASK(wem, mask_len) ((wem)->masks + 3 * (mask_len))
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/qemu/hw/ppc/ |
H A D | spapr_rtas_ddw.c | 72 const struct { int shift; uint32_t mask; } masks[] = { in spapr_page_mask_to_query_mask() local 84 for (i = 0; i < ARRAY_SIZE(masks); ++i) { in spapr_page_mask_to_query_mask() 85 if (page_mask & (1ULL << masks[i].shift)) { in spapr_page_mask_to_query_mask() 86 mask |= masks[i].mask; in spapr_page_mask_to_query_mask()
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/qemu/tests/qtest/ |
H A D | aspeed_hace-test.c | 444 struct masks { struct 450 static const struct masks ast2600_masks = { argument 456 static const struct masks ast2500_masks = { 462 static const struct masks ast2400_masks = { 469 const struct masks *expected) in test_addresses()
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/qemu/tests/functional/acpi-bits/bits-tests/ |
H A D | testcpuid.py2 | 48 masks = map(find_mask, [eax_mask, ebx_mask, ecx_mask, edx_mask]) 52 …s = bits.cpuid_result(*[(r >> shift) & m for r, m in zip(bits.cpuid(cpu, function, index), masks)]) 61 shifted_masks = bits.cpuid_result(*[m << shift for m in masks])
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/qemu/hw/audio/ |
H A D | ac97.c | 204 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT}; in update_sr() local 233 s->glob_sta |= masks[r - s->bm_regs]; in update_sr() 237 s->glob_sta &= ~masks[r - s->bm_regs]; in update_sr()
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/qemu/docs/system/s390x/ |
H A D | vfio-ap.rst | 222 driver(s). The sysfs locations of the masks are:: 256 By default, the two masks are set to reserve all APQNs for use by the default 257 AP queue device drivers. There are two ways the default masks can be changed: 297 2. The masks can also be changed at boot time via parameters on the kernel 302 This would create the following masks:
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/qemu/docs/specs/ |
H A D | rocker.rst | 311 packet data is network-byte order. For example, flow match fields (and masks)
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/qemu/target/ppc/translate/ |
H A D | vmx-impl.c.inc | 1529 /* Experimental testing shows that hardware masks the immediate. */ 1600 * to gather the bits. The masks can be created with
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 2794 /* Look for bit masks. */
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/qemu/tcg/ppc/ |
H A D | tcg-target.c.inc | 1202 /* Load common masks with 2 insns. */
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